sanny Posted November 9, 2017 Share Posted November 9, 2017 Hi, I've got two questions, which might be related. The Altirra manual in section 2.3 states that there are 114 CPU cycles per scan line. I've written a test program which disables Antic, DMA, and everything. Then it changes the background color register while the screen is displayed. This test program needs to consume 105 cycles per scan line, otherwise the display gets distorted. This is my first question. Is the Altirra manual wrong, or where do I lose the 9 (114-105) cycles? For the second question look at the attached screen shot. I expected the vertical bars to be evenly spaced. I'm doing this in the program ; this should give evenly spaced horizontal bars ; but somehow that's not the case !?? CYCLES 33 STX COLBK ; 4 cycles (37) STA COLBK ; 4 cycles (41) STX COLBK ; 4 cycles (45) STA COLBK ; 4 cycles (49) STX COLBK ; 4 cycles (53) STA COLBK ; 4 cycles (57) STX COLBK ; 4 cycles (61) STA COLBK ; 4 cycles (65) STX COLBK ; 4 cycles (69) STA COLBK ; 4 cycles (73) STX COLBK ; 4 cycles (77) STA COLBK ; 4 cycles (81) STX COLBK ; 4 cycles (85) STA COLBK ; 4 cycles (89) STX COLBK ; 4 cycles (93) STA COLBK ; 4 cycles (97) STX COLBK ; 4 cycles (101) STA COLBK ; 4 cycles (105) -> 105 cycles total This is for one display line. The code is repeated a few times to get "bars". On the right half of the screen this looks like expected. But on the left half, the bars are thicker and the space between them is also larger. Can someone explain this effect to me? Maybe my missing cycles are somehow consumed by these bigger bars and spaces btw. them. Attached are a precompiled exe and the (cc65) source code. regards, chris test.xex cycletest.zip 1 Quote Link to comment Share on other sites More sharing options...
flashjazzcat Posted November 9, 2017 Share Posted November 9, 2017 (edited) DRAM refresh still happens even if you disable DMA, and that consumes 9 cycles most of the time. I'm guessing that'll explain the uneven bar spacing too. Edited November 9, 2017 by flashjazzcat 2 Quote Link to comment Share on other sites More sharing options...
Xuel Posted November 9, 2017 Share Posted November 9, 2017 (edited) I second what flashjazzcat said. You can see all refresh and DMA cycles in Altirra by pressing Shift-F8. If you do that when DMA is completely disabled you see the following pattern: Notice that the positions of the DRAM refresh cycles correspond to the area where your bars are distorted. Maybe you could even out the bars by intermixing ST* ABS, ST* ABS,Y and STA (ZP),Y instructions to adjust the width by one or two cycles at opportune moments since those take 4, 5 and 6 cycles respectively. You could also get 7 cycles if you force a page boundary to be crossed. Edited November 9, 2017 by Xuel 2 Quote Link to comment Share on other sites More sharing options...
_The Doctor__ Posted November 9, 2017 Share Posted November 9, 2017 (edited) I think he wants to get as much out of each line as possible and wants to know how to get it all. so what is the answer 105 yes? and we are losing 9 instead of 8? why is there a difference pal/ntsc? covering the bases here... Edited November 9, 2017 by _The Doctor__ Quote Link to comment Share on other sites More sharing options...
Xuel Posted November 9, 2017 Share Posted November 9, 2017 There's no difference in the number of cycles per line between PAL and NTSC. When DMA is disabled, DRAM refresh always consumes 9 cycles. The only time refresh takes fewer cycles is on "badlines" where some of the refresh cycles are blocked by character set index lookups depending on the width of the screen and the HSCROL status. See the timing diagrams in the Altirra Hardware Reference Manual for precise timings. 1 Quote Link to comment Share on other sites More sharing options...
Heaven/TQA Posted November 9, 2017 Share Posted November 9, 2017 Interesting so the claim 114 cycles for code is wrong? Quote Link to comment Share on other sites More sharing options...
emkay Posted November 9, 2017 Share Posted November 9, 2017 Interesting so the claim 114 cycles for code is wrong? As I wrote in an other thread... Quote Link to comment Share on other sites More sharing options...
sanny Posted November 9, 2017 Author Share Posted November 9, 2017 I think he wants to get as much out of each line as possible and wants to know how to get it all. Yes, that was the reason for my question. Thanks for you answers. Now I know there's nothing wrong with my program and that there are only 105 cycles available per scan line. 1 Quote Link to comment Share on other sites More sharing options...
+Stephen Posted November 9, 2017 Share Posted November 9, 2017 Yes, that was the reason for my question. Thanks for you answers. Now I know there's nothing wrong with my program and that there are only 105 cycles available per scan line. 4 Quote Link to comment Share on other sites More sharing options...
_The Doctor__ Posted November 10, 2017 Share Posted November 10, 2017 ah but debates about what can be done with badlines or re working the the systems might surface ..... Quote Link to comment Share on other sites More sharing options...
pirx Posted November 10, 2017 Share Posted November 10, 2017 Now I know there's nothing wrong with my program and that there are only 105 cycles available per scan line. apparently a scam line Quote Link to comment Share on other sites More sharing options...
Rybags Posted November 10, 2017 Share Posted November 10, 2017 (edited) There's 114. A cycle is a cycle whether it's stolen or not. The exact cycles lost will vary depending on graphics mode, if HScrolling going on etc. This thread needs some hipster jokes... Edited November 10, 2017 by Rybags 2 Quote Link to comment Share on other sites More sharing options...
+MrFish Posted November 11, 2017 Share Posted November 11, 2017 There's 114. A cycle is a cycle whether it's stolen or not. The exact cycles lost will vary depending on graphics mode, if HScrolling going on etc. This thread needs some hipster jokes... Technically, no cycle was stolen here. 2 Quote Link to comment Share on other sites More sharing options...
flashjazzcat Posted November 11, 2017 Share Posted November 11, 2017 Precisely. The cycle pictured is not stolen, but nor is it usable. We're talking about usable cycles, of which there appear to be 105 at most. 1 Quote Link to comment Share on other sites More sharing options...
Sheddy Posted November 11, 2017 Share Posted November 11, 2017 Never were truer words spoke. Nothing stolen, but you could get pumped up thinking you had the whole 114. Bit of a let down, but we just have to handle it. Wheely a shame ..ok, not proud of that last one... 4 Quote Link to comment Share on other sites More sharing options...
flashjazzcat Posted November 11, 2017 Share Posted November 11, 2017 Thanks for that rider. 2 Quote Link to comment Share on other sites More sharing options...
Sheddy Posted November 11, 2017 Share Posted November 11, 2017 (edited) I could go on, but I'm tired now Edited November 11, 2017 by Sheddy 1 Quote Link to comment Share on other sites More sharing options...
Irgendwer Posted November 11, 2017 Share Posted November 11, 2017 That brings up the question how to disable the refresh if static RAM is used (there are some memory extensions with SRAM) - not that "fragmenting the platform" is a good thing, just for the sake of it...? Quote Link to comment Share on other sites More sharing options...
Rybags Posted November 11, 2017 Share Posted November 11, 2017 (edited) Not a lot of point really, you'd end up with an incompatible system. I suppose in doing it you'd get a "poor man's accelerated" machine with a blistering 9% or so performance increase. The logic involved would simply be taking /REF and /HALT from Antic. Whenever /REF is active, override /HALT to bring it high as seen by the CPU. But the problem is you'd also need to isolate the address bus since Antic is outputting a row address for the refresh. So the poor man's accelerator ends up being more complex/costly than a rich man's one. Edited November 11, 2017 by Rybags 2 Quote Link to comment Share on other sites More sharing options...
emkay Posted November 11, 2017 Share Posted November 11, 2017 There's 114. A cycle is a cycle whether it's stolen or not. The exact cycles lost will vary depending on graphics mode, if HScrolling going on etc. This thread needs some hipster jokes... This really looks like most cycles were stolen at a bad line. Quote Link to comment Share on other sites More sharing options...
+MrFish Posted November 11, 2017 Share Posted November 11, 2017 Precisely. The cycle pictured is not stolen, but nor is it usable. We're talking about usable cycles, of which there appear to be 105 at most. I understand what the discussion's about. My comment was meant to be humorous. Quote Link to comment Share on other sites More sharing options...
flashjazzcat Posted November 11, 2017 Share Posted November 11, 2017 I understand what the discussion's about. My comment was meant to be humorous. I know dude... so was mine. Quote Link to comment Share on other sites More sharing options...
emkay Posted November 11, 2017 Share Posted November 11, 2017 Saving CPU cycles ? Just let Antic do scrolling, shuffling Data around, let the screen shake ... Quote Link to comment Share on other sites More sharing options...
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