+mytek Posted August 21, 2018 Author Share Posted August 21, 2018 Think I'll hold off on building my 2nd XEL in favor of this new cool project I'll get New Eyes next month (cataract surgery) so I'll be able to see a whole lot better. It will allow me to stop using magnifying glasses to see. If it wasn't for my VA benefits, I'd be screwed... Just to warn you, this project will likely take much longer than the 1088XEL did. Even though I've got the board nearly ready to route, I'm holding off on doing so while I investigate some changes that I feel will make it better. And to fully investigate those changes I'm back porting them to one of my XEL boards to give it a good test. Here is a Dual Crystal Select board being done for that reason. I'm also toying around with the possibility of having independent ram for the Antic chip, so that it will no longer need to halt the CPU, which should act like a simple accelerator, hopefully one that has much better compatibility with existing software. Not sure if it's even possible, and what all will be involved, but it will be investigated none the less. Good luck with the eye surgery . 4 Quote Link to comment Share on other sites More sharing options...
+Stephen Posted August 21, 2018 Share Posted August 21, 2018 Think I'll hold off on building my 2nd XEL in favor of this new cool project I'll get New Eyes next month (cataract surgery) so I'll be able to see a whole lot better. It will allow me to stop using magnifying glasses to see. If it wasn't for my VA benefits, I'd be screwed... Good luck with the eyes. Please let me know how the surgery goes. My mom just found out the other day she has cataracts. Not quite ready for the surgery yet, but wondering and hoping it's now a pretty easy thing to do. 1 Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted August 21, 2018 Share Posted August 21, 2018 (edited) Good luck with the eyes. Please let me know how the surgery goes. My mom just found out the other day she has cataracts. Not quite ready for the surgery yet, but wondering and hoping it's now a pretty easy thing to do. Will do... My mom's boyfriend had his done a few months ago. It's a really simple procedure these days. They give you a light anesthesia that keeps you immobile so your eyes don't roll back inside your head and also stops you from blinking. They make a small incision, remove the cataract(s) ( I have 3 in each eye ), then insert the new lens and stitch it up. You are in the recovery room for an hour, then let you go home. You have to use special eye drops before and after the operation for a few days (I get mine tomorrow).. The only part that I won't like is wearing a protective cover over the eye as it'll remind me of my first eye surgery at 1 year old. They do 1 eye at a time... And thank you Edited August 21, 2018 by AtariGeezer 2 Quote Link to comment Share on other sites More sharing options...
Level42 Posted August 22, 2018 Share Posted August 22, 2018 (edited) Just to warn you, this project will likely take much longer than the 1088XEL did. Even though I've got the board nearly ready to route, I'm holding off on doing so while I investigate some changes that I feel will make it better. And to fully investigate those changes I'm back porting them to one of my XEL boards to give it a good test. Here is a Dual Crystal Select board being done for that reason. XEL_Dual_XTAL_pcb.png I'm also toying around with the possibility of having independent ram for the Antic chip, so that it will no longer need to halt the CPU, which should act like a simple accelerator, hopefully one that has much better compatibility with existing software. Not sure if it's even possible, and what all will be involved, but it will be investigated none the less. Good luck with the eye surgery . That board might be a nice upgrade for regular NTSC machines instead of having to populate the existing board with parts ? I could add an output on AntiX that could switch an external board like this....apart from the GTIA not being switched.....I wonder if wed get a color composite/s-video Signal that can be detected by most TVs ? But I bet that would also need two GTIAs. Oh and if that extra ANTIC RAM means Berzek speech can be done while the game plays on, then that is reason enough for me ???????? Edited August 22, 2018 by Level42 1 Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 23, 2018 Author Share Posted August 23, 2018 That board might be a nice upgrade for regular NTSC machines instead of having to populate the existing board with parts ? No such luck I'm afraid, since you still need the color burst crystal and sync circuit for PAL (see schematic below). This is something not normally populated on an NTSC A8 system. I could add an output on AntiX that could switch an external board like this....apart from the GTIA not being switched.....I wonder if wed get a color composite/s-video Signal that can be detected by most TVs ? But I bet that would also need two GTIAs. Yes you could switch it with a standard digital output, with NTSC = GND and PAL = +5V Correction: NTSC = +5V and PAL = GND, but you would need the matching GTIA to make sense of it. Oh and if that extra ANTIC RAM means Berzek speech can be done while the game plays on, then that is reason enough for me Speaking of independent RAM for the Antic chip... The more I look at this, the more it doesn't seem doable. Well at least not without a lot of complexity and/or cost. The ideal situation would be to use a dual port 64K x 8 SRAM, but those are mega expensive coming in around the 70-80 USD range. To try and do something with two independent SRAM chips would of course require several transceiver chips to allow the CPU to write into Antic's RAM, but then you might still have problems with Antic clobbering the CPU if it was trying to access the same exact location in address space, at the same time. A true dual port SRAM has built-in safeties to prevent this kind of conflict, whereas a home brew version would get very complicated to mimic this action. It would definitely have to be CPLD based logic to keep this to a reasonable number of components. Currently not something I have in my wheel house . 2 Quote Link to comment Share on other sites More sharing options...
ivop Posted August 23, 2018 Share Posted August 23, 2018 Wouldn't it be possible to shift the clock of the Antic 180 degrees and have Antic reads in between the CPU reads and writes? It would still need a few buffers to isolate the bus or switch the bus to Antic or the CPU, but with current SRAM speeds it should be possible, I think, to have two read/write cycles in a single clock cycle. Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 23, 2018 Author Share Posted August 23, 2018 Wouldn't it be possible to shift the clock of the Antic 180 degrees and have Antic reads in between the CPU reads and writes? It would still need a few buffers to isolate the bus or switch the bus to Antic or the CPU, but with current SRAM speeds it should be possible, I think, to have two read/write cycles in a single clock cycle. Very interesting idea. Since the Antic provides the clock to the CPU, if an inverter were placed inline with that it would essentially shift the clock by 180 degrees going to the CPU. Then I would think that the normal HALT as issued by Antic would also be shifted by 180, occurring between read-writes for the CPU. Would that be enough? I doubt it, since that would be way too easy . Quote Link to comment Share on other sites More sharing options...
ivop Posted August 23, 2018 Share Posted August 23, 2018 Not sure if that would be enough to avoid bus contention between Antic and CPU. It depends on when each of them start driving the busses. If there's an overlap, you would still need to make sure each half cycle only one is on the bus. Here's a small diagram of when I think each of them should have control over the bus to do reliable reads and writes Quote Link to comment Share on other sites More sharing options...
foft Posted August 23, 2018 Share Posted August 23, 2018 So with antic clock shifted.. An0-2 shifted Effect on cpu reads? Antic reads from rom/cart/pbi Clearly possible (and fun) but I think you are going to need much more glue! 1 Quote Link to comment Share on other sites More sharing options...
ivop Posted August 23, 2018 Share Posted August 23, 2018 (edited) Perhaps one should not shift the ANTIC clock, but only the CPU clock, so ANTIC and GTIA stay in sync? Also, I was wondering what would happen if you write to the ANTIC registers while it is in its low period, while normally you would write during the high period of the clock cycle. Edit: another thing springs to mind: if the CPU starts writing to an ANTIC register right after ANTIC did a read or refresh, the bus needs to be connected to both, possibly leading to bus contention again.... yeah, it's not that easy I'm afraid Another idea I've had for years, is feeding Pokey a slower clock (1.3-1.5MHz) like in the arcade machines. Start with normal clock for the OS/SIO to function normally. After that, have a software switch to switch to a slower clock (and back if you want to). Edit2: Dual port SRAM 64Kx8 5V €49,04 https://nl.mouser.com/Search/Refine.aspx?N=4292490764&Keyword=972-7008L15JG&utm_source=octopart&utm_medium=aggregator&utm_campaign=972-7008L15JG&utm_content=IDT%20(Integrated%20Device%20Technology) Still quite expensive. I read that Dual Port SRAM can also be implemented in FPGA. Maybe that's a cheaper route? Edited August 23, 2018 by ivop 2 Quote Link to comment Share on other sites More sharing options...
_The Doctor__ Posted August 23, 2018 Share Posted August 23, 2018 (edited) if they occur during the throw away period for either they really should ignore each others traffic, the other Idea that floated around at one point in time was to have them operate in some range that the affinity for rising edge as to falling edge might be catered to, allowing cpu and antic to access during the same clock cycle... as antic is just reading memory. Edited August 23, 2018 by _The Doctor__ 1 Quote Link to comment Share on other sites More sharing options...
+Spaced Cowboy Posted August 24, 2018 Share Posted August 24, 2018 Still quite expensive. I read that Dual Port SRAM can also be implemented in FPGA. Maybe that's a cheaper route? Dual port RAM could easily be implemented in an FPGA, but you really need to use block-ram. It's expensive (in real-estate, and therefore in dollars) to use the "distributed RAM". The cheapest Spartan-7 that would fit is the XC7S25 ($25) and the cheapest Spartan6 is the LX9 - if you used every block ram - at $16.50. The thing you have to remember about FPGAs is that they're not 5v-tolerant, so you need level-changers, separate clock, and you want a series of power-supply circuits, all gated so that they turn on in the correct sequence. The LX9 (as well as being cheaper) has the advantage of being in QFP format, so you don't need a BGA build-process. Even so, you're looking at ~$30-$35 for the BOM for the LX9 in small quantity - gate-able high-power (2A+) 1v, 1.8v, and 3.3v power supplies aren't cheap. If I might suggest - the STM32F446 might be a good fit for the job. There's plenty of on-board SRAM (128K!) , there's plenty of pins for both SRAM busses, and the ports map well to an address-bus (so a single read operation can read 16 bits at a time). I chose one that runs at 180 MHz to give ample time to respond to a ~2MHz bus, has an internal clock, is 5v-tolerant on all pins, and it boots from internal flash, so it'd pretty much be plug-in-and-go. Since it's not doing anything else, you're not tied to interrupt-latencies (12 clocks on the STMF4) for response-times, you can use BLT ("Big Loop Technology" ) to just keep on doing sample bus A if address is stable, then update SRAM on a write, or drive the correct values on bus A's lines on a read sample bus B if address is stable, then update SRAM on a write, or drive the correct values on bus B's lines on a read redo from start This gives a priority to bus B in terms of whose write wins if both want to write to the same address, but AFAIK, Antic only ever reads from the bus, so this oughtn't be an issue. Interrupt latencies were the problem I had with a CPU decoding the bus on my project - I needed the main CPU free for other things, so I was forced to use interrupts for bus management, and I didn't like the chances of hitting the bus timings perfectly by interrupting the CPU. An STM32F446VET6 is $9.51, quantity 1, in a QFP100 package. All you'd need extra would be a few caps, a cheap (500mA, no need for PGOOD or ENABLE signals) 3.3v voltage regulator, and an SWD or JTAG port for programming. Simon. 4 Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 24, 2018 Author Share Posted August 24, 2018 I like that last suggestion the best, but it's beyond my present abilities. So I was thinking that this might be handled best by making it an Antic piggyback board to be added at a later date. Nice thing about that approach, is it would also work in a standard A8 as well. 3 Quote Link to comment Share on other sites More sharing options...
ivop Posted August 24, 2018 Share Posted August 24, 2018 Here's another idea: CPU has RAMA (64kB) ANTIC has RAMB (64kB) CPU reads and writes to RAMA at its normal time during a clock cycle ANTIC reads RAMB at its normal time At the beginning of a new cycle (after reads and writes), ANTIC gets disconnected from RAMB and a quick write cycle is done to RAMB with the buffered contents of the address and data bus of the CPU (i.e. replay what the CPU did to RAMA). You can always do a write cycle, even if the CPU did a read. Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 24, 2018 Author Share Posted August 24, 2018 Here's another idea: CPU has RAMA (64kB) ANTIC has RAMB (64kB) CPU reads and writes to RAMA at its normal time during a clock cycle ANTIC reads RAMB at its normal time At the beginning of a new cycle (after reads and writes), ANTIC gets disconnected from RAMB and a quick write cycle is done to RAMB with the buffered contents of the address and data bus of the CPU (i.e. replay what the CPU did to RAMA). You can always do a write cycle, even if the CPU did a read. Yes this could likely work. However still requires quite a bit of glue to do the transfer from one RAM to the other if we are talking about using two actual 64K x 8 SRAMs. Are we still looking at using the STM chip and it's internal RAM for this purpose? Quote Link to comment Share on other sites More sharing options...
ivop Posted August 24, 2018 Share Posted August 24, 2018 Yes this could likely work. However still requires quite a bit of glue to do the transfer from one RAM to the other if we are talking about using two actual 64K x 8 SRAMs. Are we still looking at using the STM chip and it's internal RAM for this purpose? Both is an option, I guess. It should be doable with three octal multiplexers (for bus selection), three octal buffers and a shifted clock to trigger the switch busses and replay. Hmm, that's quite a lot of IC's already. Maybe a CPLD and an LS123 could do the same. I think the STM route is be easier. The Uno Cart source code might come in handy, as it already contains code to run-the-bus. I actually prefer this, because you can simply code in C or ARM assembly, instead of verilog/vhdl (which I do not know much about ) 1 Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 24, 2018 Author Share Posted August 24, 2018 As I mentioned already, this would be a good upgrade to make in a more universal form, and not limited to the 1088XLD project. To that end it would be best if it could be kept small, so that it would fit inside a normal A8 system with a piggy-back approach being preferred, since that could be a solder-less installation (or nearly so). I would be happy to do the PCB layout, but I would have to pass on the programming aspect. 4 Quote Link to comment Share on other sites More sharing options...
ivop Posted August 24, 2018 Share Posted August 24, 2018 I agree. A piggyback board would be the way to go. Oh, so many ideas Anyway, it's good that we discussed it here a little and found out what problems there are to overcome. Quote Link to comment Share on other sites More sharing options...
+Spaced Cowboy Posted August 24, 2018 Share Posted August 24, 2018 I would be happy to do the PCB layout, but I would have to pass on the programming aspect. I'd volunteer, but I'm pretty sure there's already plenty on my plate for the forseeable future Question: How do you do a piggy-back board for Antic's bus-lines, if it's soldered into the motherboard ? Or is it never soldered, and you can just pull it out of the socket and put it into a socket on the piggy-back board ? Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 24, 2018 Author Share Posted August 24, 2018 I agree. A piggyback board would be the way to go. Oh, so many ideas Anyway, it's good that we discussed it here a little and found out what problems there are to overcome. I'll start a new topic for this in a little bit, since it appears to be something of a much more stand-alone nature. And as such, really deserves to have a dedicated thread. Anyone thought of a name for it? I'd volunteer, but I'm pretty sure there's already plenty on my plate for the forseeable future Yeah that's for sure . But thanks for the interest. Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 31, 2018 Author Share Posted August 31, 2018 First PCB created for the project. This board provides the front panel interface connectors and status LEDs. From Left to Right: Stereo Headphone Jack, Stereo and V-Gate indicators, Mouse, Keyboard, Mouse Port 2 Indicator, Joystick 2, Joystick 1, Mouse Port 1 Indicator It's a simple one, but at least it's a start . 9 Quote Link to comment Share on other sites More sharing options...
+mytek Posted September 8, 2018 Author Share Posted September 8, 2018 There will be a dedicated header for plugging in a DreamBlaster S2 wave table board. Circuit Schematic I did some playing around with this over the last few days, and it looks like this will be a nice asset to incorporate into the 1088XLD. However I discovered in those initial tests that it's not a good idea to gate the power to the MIDI module as a means of removing it from the SIO. That method of severing communications was causing a noticeable glitch in the audio at the end of a song, and also terminating the last notes prematurely as they faded out. So instead the power will be fixed, and the MIDI-IN signal will get disconnected (gated) from the SIO Data-Out. This allows any sustained notes to complete, and also allows for a clean ending. System RESET is provided to the module as a way to recover if the module were ever to lock up (hasn't happened to me yet... but just in case). Since I'm designing the 1088XLD from the ground up, I decided it would be better to derive the MIDI gating signal directly from the PIA output rather than from the PNP transistor connected to the SIO's cassette motor control. Although with the PIA signal being inverted from the normal motor control output (LOW = ON), it'll pass through one NAND gate before being used as the 'enable' signal to yet another for gating the MIDI communication. I'm still kicking around the possibility of also including a 31250 hz MIDI baudrate clock to SIO Clock-In, but haven't decided upon that just yet. The DreamBlaster seems to be fine without it thus far. However there may be a way to kill 2 birds with one stone if I take the PIC MCU approach, and do both the MIDI communications gating and baudrate clock in a single programmed 8-pin device. We'll see . 4 Quote Link to comment Share on other sites More sharing options...
ivop Posted September 8, 2018 Share Posted September 8, 2018 (edited) Nice idea! This actually improves on the MIDI Max/Mate/Muse idea, though IIRC one of the R-Verter incarnations were also always-on and connect/disconnect the SIO RX/TX lines according to motor control. Edit: IMHO you should include the exact MIDI baudrate. Optocoupler and DIN5 IN/OUT/Thru can live on the add-on board with angle brackets. Edited September 8, 2018 by ivop 2 Quote Link to comment Share on other sites More sharing options...
+mytek Posted September 8, 2018 Author Share Posted September 8, 2018 Nice idea! This actually improves on the MIDI Max/Mate/Muse idea, though IIRC one of the R-Verter incarnations were also always-on and connect/disconnect the SIO RX/TX lines according to motor control. Edit: IMHO you should include the exact MIDI baudrate. Optocoupler and DIN5 IN/OUT/Thru can live on the add-on board with angle brackets. Yep that's where I got the gating idea from, when I was reading the ESP wifi thread the other day. And yes I decided that incorporating the MIDI baudrate clock onto my main board would make sense, especially since there are some programs that require it. I'm still liking the idea of maybe doing the gating and the baudrate clock in something like a PIC12F1571. Running this at 32 Mhz via the built-in PLL, would give me an instruction cycle time of 31 nSec which should be more then fine at passing through MIDI data and/or gating it. And if I use an 8 Mhz crystal to clock the PIC, that can be divided down to 31250 hz and sent out the PWM pin with a 50/50 duty cycle. So on paper this would end up being composed of one 8-pin chip plus a crystal. Pretty simple. Next on the agenda would be to develop a much nicer MIDI player. Even better still if it were FAT based so you could have long file names. Being limited to 8 characters is not going to work if someone wants to a have a large library of songs, with the only option being some sort of numbering system which would be very cryptic. Edit: Unfortunately making such a player is quite a bit beyond my comfort zone and/or abilities. 3 Quote Link to comment Share on other sites More sharing options...
ivop Posted September 9, 2018 Share Posted September 9, 2018 Was just thinking about this and two things came to mind: 1. Separation of digital and analog ground/+5V. (Perhaps something that should be considered for the whole board?) 2. Means to deliver +12V/-12V to a connected WaveBlaster board. This could be catered for by a pin header if somebody really needs +/-12V for their WB board (some do BTW!). But no need for 12V on the main board IMHO. Unless you want to deliver +12V on SIO pin 12 Quote Link to comment Share on other sites More sharing options...
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