24 replies to this topic

[supercat]

In considering the design of a CMOS-based 6502 clone, one issue I would consider important would be determining which instructions need to be emulated with what degree of trickiness.  Designing a CMOS circuit to emulate all the intricacies that occur when the ARR instruction is executed with the decimal flag is set would be a challenge almost comprable to designing a chip to do everything else.  Consequently, I would think it might be interesting to know what instructions people actually use.

My personal feeling is that any 6502 clone seeking 2600 compatibility should probably support the opcodes listed above except for the decimal-related quirks of ARR.  As I see it, the opcodes divide into the following groups:

-1- ALU+RMW -- The opcode of an ALU operation for anything other than immediate mode, plus $20, performs the RMW operation of that opcode plus $10 and then performs the instruction

-2- LAX/SAX -- Enabling Accumulator and X register simultaneously for loads/stores.

-3- SBX -- Something of an oddball

-4- ALW+RMW immed -- These behave a bit differently from other ALU+RMW instructions, and also from each other

-5- LAS (and TAS)

Anything else people use?

[batari]

supercat, on Sun Jan 7, 2007 8:21 PM, said:

In considering the design of a CMOS-based 6502 clone, one issue I would consider important would be determining which instructions need to be emulated with what degree of trickiness.  Designing a CMOS circuit to emulate all the intricacies that occur when the ARR instruction is executed with the decimal flag is set would be a challenge almost comprable to designing a chip to do everything else.  Consequently, I would think it might be interesting to know what instructions people actually use.

My personal feeling is that any 6502 clone seeking 2600 compatibility should probably support the opcodes listed above except for the decimal-related quirks of ARR.  As I see it, the opcodes divide into the following groups:

-1- ALU+RMW -- The opcode of an ALU operation for anything other than immediate mode, plus $20, performs the RMW operation of that opcode plus $10 and then performs the instruction

-2- LAX/SAX -- Enabling Accumulator and X register simultaneously for loads/stores.

-3- SBX -- Something of an oddball

-4- ALW+RMW immed -- These behave a bit differently from other ALU+RMW instructions, and also from each other

-5- LAS (and TAS)

Anything else people use?

I don't use anything you haven't listed in this message, but I can't vote in the poll because SBX isn't in there...

[supercat]

batari, on Sun Jan 7, 2007 11:45 PM, said:

I don't use anything you haven't listed in this message, but I can't vote in the poll because SBX isn't in there...

Sure it is.  Last item "Other"

I would have liked to have a "yes/no" poll on all the instructions.  So which ones have you used?  I haven't used all of the ALU+RMW combos, but I have used DCP, ISC, and I think RLA as well as ALR.  I've also used LAX, SAX extensively, and SBX a little bit.  An experimental version of my TT kernel even used LAS but I decided I didn't want to waste the fifteen bytes of RAM to make it work (it would have saved two cycles).

For that matter, which NOPs have you used?  TT uses NOP abs, NOP #imm, and NOP zp; I've also on occasion used NOP abs,x and even an undocumented one-byte two-cycle nop(!).

[batari]

supercat, on Mon Jan 8, 2007 12:52 AM, said:

batari, on Sun Jan 7, 2007 11:45 PM, said:

I don't use anything you haven't listed in this message, but I can't vote in the poll because SBX isn't in there...

Sure it is.  Last item "Other"

I would have liked to have a "yes/no" poll on all the instructions.  So which ones have you used?  I haven't used all of the ALU+RMW combos, but I have used DCP, ISC, and I think RLA as well as ALR.  I've also used LAX, SAX extensively, and SBX a little bit.  An experimental version of my TT kernel even used LAS but I decided I didn't want to waste the fifteen bytes of RAM to make it work (it would have saved two cycles).

For that matter, which NOPs have you used?  TT uses NOP abs, NOP #imm, and NOP zp; I've also on occasion used NOP abs,x and even an undocumented one-byte two-cycle nop(!).

bB uses SBX, LAX, ASR, DCP, and NOP Abs and ZP.  In an earlier game I used some of the above, plus SAX, ISB and ARR.  I used ANC for something (can't remember what) and NOP Abs,x (or maybe it was y) for bankswitching at one point but it's not in anything the world has seen.  Although I have not used SLO, SRE, RLA or RRA, I could see myself using them if the situation were right.

I agree that the ARR decimal mode is probably not needed.  However, I can't see a lot of real utility for SHS, SHA, SHY and SHX either, and ANE and LXA seem to be unstable, so nobody's likely to use them.

I just read up on LAS, and it seems really obscure to me.  How did you use this?

[supercat]

batari, on Mon Jan 8, 2007 1:23 AM, said:

I just read up on LAS, and it seems really obscure to me.  How did you use this?

I need to mask the last GRP1 value I store with a variable quantity, after I've loaded it using (ind),y mode.  Because there is an "LAX (ind),Y" instruction but no "LDX (ind),Y" the last GRP1 and COLUP1 values need to be in X and S.

I don't remember exactly how I worked things, but the LAS instruction provided a way to move the stack pointer into the accumulator while masking it with another value.  Unfortunately, because it only supports abs,Y mode it was necessary to store the mask value into fifteen consecutive addresses.  Even though LAS saved a couple cycles, the loss of 15 bytes of RAM wasn't worth it.

[Thomas Jentzsch]

LAX for me.

[Simon]

No interest in illegal opcodes on my side... never used, never will. :-)

[Zach]

Sympathy vote for SHX. It is actually likely to end up in my latest project, as soon as I'm convinced it's completely safe.

BTW: I like the term bonus much better than illegal.

Edited by Zach, Mon Jan 8, 2007 9:39 AM.

[Bruce Tomlin]

I used LAX in my red box/blue box touch-tone dialer to save a few cycles in my sine wave table lookup macro.  Since it was executed every scanline, it made a real difference.

FWIW, in my own assembler, I support the following "bonus" instructions:

NOP3 - 3 cycle NOP: $04,$00
LAX abs, zpg, inx, iny, aby, zpy
DCP abs, zpg, inx, iny, zpx, abx, aby
ISB abs, zpg, inx, iny, zpx, abx, aby
RLA abs, zpg, inx, iny, zpx, abx, aby
RRA abs, zpg, inx, iny, zpx, abx, aby
SAX abs, zpg, inx, zpy
SLO abs, zpg, inx, iny, zpx, abx, aby
SRE abs, zpg, inx, iny, zpx, abx, aby
ANC imm
ARR imm
ASR imm
SBX imm



YOU CAN GET BONUS! With sign up bonus code 6507!  20% up to 100 cycles!

Edited by Bruce Tomlin, Mon Jan 8, 2007 10:11 AM.

[SpiceWare]

Simon, on Mon Jan 8, 2007 4:41 AM, said:

No interest in illegal opcodes on my side... never used, never will. :-)

not even a 3 cycle NOP?

[Cybergoth]

Hm... so far I only use LAX, DCP and NOPs. I think DCP is my favourite

[supercat]

Bruce Tomlin, on Mon Jan 8, 2007 9:55 AM, said:

FWIW, in my own assembler, I support the following "bonus" instructions:

No "NOP abs" or "NOP abs,x"?  In many bankswitching modes "NOP abs" can be useful (though to be sure CMP or BIT is probably just as good); in 4A50, "NOP abs,x" and "NOP zp" can be useful as well.

[Simon]

SpiceWare, on Mon Jan 8, 2007 9:12 PM, said:

Simon, on Mon Jan 8, 2007 4:41 AM, said:

No interest in illegal opcodes on my side... never used, never will. :-)

not even a 3 cycle NOP?

No, thanks. I prefer keeping programming limited to the "official" set of instructions. BIT works fine for 3 cycles...

[vdub_bobby]

I probably use the extra modes of NOP most often, followed by DCP.  Maybe use DCP more often.  I voted DCP for that reason, though I think LAX is the coolest.

[Cybergoth]

vdub_bobby, on Tue Jan 9, 2007 7:14 PM, said:

I probably use the extra modes of NOP most often, followed by DCP.  Maybe use DCP more often.  I voted DCP for that reason, though I think LAX is the coolest.

LAX is the one that I already use automatically, without spending much thought on it. Even outside the kernel, wherever I see it fit. In most of my recent projects I gained the most kernel-boost from DCP though. Illegal NOPs just come and go with the SLEEP macro

BTW: Illegal opcodes also work on the 6510, not just 650x

[Heaven/TQA]

i never used any of the illegal opcodes... i can understand DCP and LAX or TOP,DOP but please can someone explain me the usability of the others? ehm...should have read my website... http://www.s-direktn...dj/opcodes.html

Edited by Heaven/TQA, Tue Jan 9, 2007 3:23 PM.

[vdub_bobby]

Looking through the list of illegal ops, just noticed XAA.  Is that one stable?

That could be pretty useful, replacing:

   txa
   and #7
   tay

with

   xaa #7
   tay

Or replacing

   txa
   and #$0F
   bne Somewhere

with

   xaa #$0F
   bne Somewhere

[batari]

vdub_bobby, on Tue Jan 9, 2007 5:33 PM, said:

Looking through the list of illegal ops, just noticed XAA.  Is that one stable?

That's $8B, which is also called ANE.  It seems to be unstable.

[vdub_bobby]

Bummer...

[supercat]

Heaven/TQA, on Tue Jan 9, 2007 3:21 PM, said:

i can understand DCP and LAX or TOP,DOP but please can someone explain me the usability of the others? ehm...should have read my website...

The "bonus" opcodes weren't put on the chip to be useful.  They behave as they do because having them behave differently would probably have required extra circuitry (or would have required rearranging some other things).

As a simple example, consider "LAX" and "SAX" (the latter is called ASX I think in your documents).  To understand these, notice that "LDY", "LDX", and "LDA" as well as "STY", "STX", and "STA" all follow a pattern.  Two bits indicate which register is to be loaded or stored.  These bits are "nor'ed" together to generate a select signal for the "Y" register, while the bits themselves generate select signals for the "A" and "X" registers.  LAX and SAX are like the other LD* and ST* instructions except that both of these bits are set.

In the case of "LAX", selecting both registers at once causes both registers to be loaded with the contents of the data bus.  Note that LAX does not work in immediate mode, for reasons I'll touch on shortly.  SAX is a bit more interesting.  It causes both the accumulator and X register to try to output their values simultaneously onto the ALU bus (which in turn drives the data bus).  In a CMOS device (today's technology) this would be very bad.  In NMOS, however, (as used in the 1970's) it's pretty harmless.  Rather than try to include circuitry to fully determine whether each signal should be high or low, NMOS devices typically use a resistor to pull signals high by default and then only drive them low if needed.  So the ALU bus in the 650x probably has the accumulator, X register, and Y register set so they can pull appropriate bits low; if none of them pulls a bit low, it will be high.  SAX then allows both the X register and teh accumulator to pull down the bits they each "think" should be low.

The case of LAX #imm is interesting.  What happens there is that the designers of the 6502 decided to use $AA as the opcode for TAX.  Since they noticed that $AB wasn't a legitimate opcode, they figured that any opcode whose most-significant 7 bits were "1010101" must be TAX.

One might at first wonder why this would be a problem.  After all, if it weren't for the TAX behavior the LAX #imm instruction would load A and X with the same value; transfering A to X shouldn't affect anything.

The problem is that the instruction creates a feedback path which may capture glitches when circuits don't switch cleanly.  Normally there's no problem if things don't switch cleanly.  If the "TAX" instruction loads an incorrect value into the X register for a brief moment before it loads the correct value, there's no problem.  The value will be correct long before anything tries to use it.  Combining "LAX" and "TAX", however, creates a problem.  If the accumulator briefly gets loaded with an incorrect value, that value will be routed to the register-input bus along with the signal from the data bus.  If the value has become correct before the wrong value has propagated through the circuitry necessary to reach the register input, that result will start propagating.  In theory, the right and wrong results could keep circulating around and around inside the chip.  In practice, one or the other will 'win' in pretty short order, though the outcome of the race may be unpredictable.

BTW, one thing that amazes me with the 650x is that instructions like "DCP" get sequenced correctly so as to avoid such race conditions.  My guess would be that the state machine of the 6502 is constructed in such a way that read-modify-write and ALU-accumulator opcodes run through a common state machine that uses different states for the three RMW steps and the ALU step; typically the unnecessary states are skipped, but they exist in the state machine anyway.  Something of a different sequence from the accumulator-mode RMW instructions which behave oddly when combined with immediates for reasons I don't understand (e.g. why does ALR store the shifted value into the accumulator, but ANC does not?)

[supercat]

batari, on Tue Jan 9, 2007 4:55 PM, said:

That's $8B, which is also called ANE.  It seems to be unstable.

Opcode $8B combines "SAX #immediate" with "TXA".  Although the behavior isn't quite the same as $AB, it sufferes from the same feedback problems.

[batari]

supercat, on Tue Jan 9, 2007 6:57 PM, said:

batari, on Tue Jan 9, 2007 4:55 PM, said:

That's $8B, which is also called ANE.  It seems to be unstable.

Opcode $8B combines "SAX #immediate" with "TXA".  Although the behavior isn't quite the same as $AB, it sufferes from the same feedback problems.

Come to think of it, regardless of the instability of $AB (LXA), could it be used to reliably load both A and X with zero in two cycles?  If the worst that could happen is an unintentional ANDing, loading with zero would still work.  I've often had a need to do that but "LAX" lacks the addressing mode.

[supercat]

batari, on Tue Jan 9, 2007 7:28 PM, said:

Come to think of it, regardless of the instability of $AB (LXA), could it be used to reliably load both A and X with zero in two cycles?  If the worst that could happen is an unintentional ANDing, loading with zero would still work.  I've often had a need to do that but "LAX" lacks the addressing mode.

Some of the unstable opcodes turn bits into "1"'s that seemingly should be zeroes.  If I had a 650x schematic I might be able to ascertain what aspects of those instructions should be considered predictable, but I don't know Dutch (or was it German)?

[ijor]

supercat, on Tue Jan 9, 2007 9:56 PM, said:

If I had a 650x schematic I might be able to ascertain what aspects of those instructions should be considered predictable, but I don't know Dutch (or was it German)?

Hungarian.

But when I checked, it seems there weren't full schematics there yet. Only full micro photographs and partial schematics. But you can guess that my Hungarian is not better than yours, so I can't be sure

[supercat]

ijor, on Sat Jan 13, 2007 9:31 AM, said:

But when I checked, it seems there weren't full schematics there yet. Only full micro photographs and partial schematics. But you can guess that my Hungarian is not better than yours, so I can't be sure

BTW, do any photos exist of the TIA?  It would be pretty neat to be able to see how different structures were realized on silicon.

Among other things, I'm curious about the data bus wiring and the playfield circuit.  Looking at the schematic, it's clear that the playfield circuit was designed to minimize routing.  But I would think that the effort required to route data bus pins everywhere else would make that advantage comparatively slight.

Edited by supercat, Sat Jan 13, 2007 1:32 PM.