That's just changing the VBI vector.
Probably masks the Reset key because it just does an RTI... without pulling the registers... which would result in a crash fairly quickly.
Since 400/800 doesn't have a Hard Reset, it becomes an unrecoverable lockup.
Trust me - there's absolutely no way to disable the System Reset key on a standard 400/800 without modding the machine itself, or without crashing the machine.
I remember one funny old trick to cause Reset to give an unusable machine without crashing it - set APPMHI ($E,F) to a value above where the screen starts. It means that the E: device can't open when you press Reset - doesn't work on XL as they discovered the bug by then and fixed it.
It's still useful if you wanted to show an image on the screen and disallow anyone coming and hitting the reset.
I'll try to dig up the one that allows you to execute code and disallow the reset.
That APPMHI would still execute code when RESET is pressed so it wouldn't be a complete lockout.
Here's the code I dug up for complete SYSTEM RESET lockout on Atari 400/800 (this compiles to a boot disk of 242 bytes):
;*** ATIRQ400.asm: Atari Timer IRQ measured to exact cycles so no WSYNC is required by Krishna Software Inc.
;*** This plays music on voice #1 and uses IRQ timer interrupt on timer #4. Voice #0 is for constant tone.
;*** There are three CLKs which can be used by either 8 or 16 bit divisors as controlled by 53768.
;*** The 15.6999Khz CLK and 63.921Khz CLK can be turned off via 53775 but 1.78979Mhz CLK is always on.
;*** The 15.6999Khz CLK is 1.78979Mhz/114 and gives the scanline interrupt at end of scanline.
;*** The 63.921Khz CLK is 1.78979Mhz/28 and does not divide evenly into 29868 cycles/frame so cannot be used
;*** for color clock accurate or scanline accurate interrupts. This program also attempts to write IRQ vector
;*** directly at 65534/65535 by disabling ROM for XL/XE series (should have no effect on Atari 400/800).
;*** This program locks out SYSTEM RESET on Atari 400/800 where it's a NMI.
TIMERFREQLSB = 53760
TIMERFREQMSB = 53762
WSYNC = 54282
VCOUNT = 54283
DOSVEC = 10
CASINI = 2
WARMSTART = 58484
VMIRQ = 534 ;hardware irq ptr
ORG = 600h
DB 0,3 ;# of sectors to load 1..255
StartAdr: Lda #MyReset,L
MyReset: Lda #2
Lda #0 ;no VBIs nor DLIs for maximum performance
Sta 53774 ;disable all IRQs
Sta 54272 ;turn off screen
Sta 54017 ;disable ROM and BASIC for XL/XE series via PORTB
Lda #TimerTwoIRQ,L ;general IRQ routine but we use only for timer #2
Sta SelfModifyThis+1 ;Remove 5 cycles from background task (for Jmp )
ROMVectorSet: Lda #40 ;+40 for join channels 3,4; +80 for channels 1+2 @1.79Mhz
Sta 53768 ;join channels at 1.79 Mhz
Lda #114-7 ;lsb 114-7 or 57-7 for two irqs/scanline
Sta 53764 ;timer #2 freq = 1789790/[A+1]
Lda #0 ;msb for rate divisor A
Lda #4 ;1,2,4=timer interrupts
Sta 53774 ;enable IRQ #2
;Sta 53248 ;unrem to show sprite using 0 CPU cycles and 0 DMA cycles
Ldy #4 ;load ack parameters
NotMidScr: Cmp VCOUNT
Bne NotMidScr ;CF=1 when A=65
Sta 53769 ;start timer counter
IdleLoop: ;(29868 cycles in NTSC frame - 9*262 for Refresh = 27510 cycles so to keep the IRQ
; stable, cycles must be aligned to 27510 including IRQ routine). For PAL frame, use
; 312*114 = 35568 - 312*9 = 32760 cycles.)
;(27510 factors to 2*5*7*3*131)
;Lda 53770 ;No longer random if bits 0,1 of 53775 = 0
Sta 53762 ;make construction site noise
Lda #64 ;which of these two instruction to rem out depends on IRQ routine total cycles
SelfModifyThis: Jmp Idle1 ;For Atari 400/800, this jmp and following NOP (5 cycles) will be removed since ROM vector not used
;*** H/W does jmp  (7 cycles) and XL/XE OS does a CLD and JMP  for 2+5 = 7 cycles.
;*** Below routine 32 cycles+7+5 = 44 cycles on old OS (like on Atari 400/800).
;*** Optimized by using X/Y registers and not using it in main routine so PHA/PLA not needed.
TimerTwoIRQ: ;Pha ;3 cycles
;Sta 53771 ;POTGO
Inc 53274 ;change register (like color for example)
;Sta 53774 ;send ack to timer irq (optimized with Inc = 6 cycles)
Sty 53774 ;do ack
Ror 53274 ;change register (like color for example)
;Pla ;4 cycles
Rti ;6 cycles
;LastOffset: DW 2e0h,2e1h,ORG