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Luma Enhancement Module Development


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#51 ClausB OFFLINE  

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Posted Fri Oct 30, 2009 4:57 AM

The timing diagram shows the SRAM but not the LUMA timing. (does it?) While we are loading one register, are we reading LUMA from the other? In the next/same cycle?

Right. I was thinking we should read the luma from the second register right away for one cycle and then, on the next (non-DMA) cycle, transfer the first register to the second and then read it out. That way we're only multiplexing 8 bits every cycle instead of 16 bits every two cycles. Also, by reading out the second register first, we eliminate ~0.5 color-clock delay between luma and GTIA which I measured on the prototype (see old thread).

I was thinking yesterday that we could also eliminate the full 8 color-clock (4 cycle) delay by chaining 4 more 8-bit registers and clocking the luma data through them every cycle. That would make the luma output line up with the GTIA output so the programmer would not have to offset the luma plotting. Also the character modes (above) would work better. It takes 32 more flip-flops, but you said you had some 64 FF CPLDs, right?

#52 ClausB OFFLINE  

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Posted Fri Oct 30, 2009 5:52 AM

Here's a truth table for the luma multiplexer output. As I said, we divide the Phi2 cycle into 8 70 ns states to drive the mux and select data bits as luma outputs:

Mode 0: black (all outputs 0), LEM disabled
 
Mode 1: all 16 gray levels, 160 pixels
State  0  1  2  3  4  5  6  7
Lum3  D7 D7 D7 D7 D3 D3 D3 D3
Lum2  D6 D6 D6 D6 D2 D2 D2 D2
Lum1  D5 D5 D5 D5 D1 D1 D1 D1
Lum0  D4 D4 D4 D4 D0 D0 D0 D0
 
Mode 2: 4 levels (0, 5, A, F), 320 pixels
State  0  1  2  3  4  5  6  7
Lum3  D7 D7 D5 D5 D3 D3 D1 D1
Lum2  D6 D6 D4 D4 D2 D2 D0 D0
Lum1  D7 D7 D5 D5 D3 D3 D1 D1
Lum0  D6 D6 D4 D4 D2 D2 D0 D0
 
Mode 3: 2 levels (0, F), 640 pixels
State  0  1  2  3  4  5  6  7
Lum3  D7 D6 D5 D4 D3 D2 D1 D0
Lum2  D7 D6 D5 D4 D3 D2 D1 D0
Lum1  D7 D6 D5 D4 D3 D2 D1 D0
Lum0  D7 D6 D5 D4 D3 D2 D1 D0


#53 bob1200xl OFFLINE  

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Posted Fri Oct 30, 2009 6:09 PM

Yes. The 44 pin 1504s have 64 F/Fs and 36 I/O pins.

So, you want a 32 bit delay in LUMA output? 8 color clocks?

Bob




The timing diagram shows the SRAM but not the LUMA timing. (does it?) While we are loading one register, are we reading LUMA from the other? In the next/same cycle?

Right. I was thinking we should read the luma from the second register right away for one cycle and then, on the next (non-DMA) cycle, transfer the first register to the second and then read it out. That way we're only multiplexing 8 bits every cycle instead of 16 bits every two cycles. Also, by reading out the second register first, we eliminate ~0.5 color-clock delay between luma and GTIA which I measured on the prototype (see old thread).

I was thinking yesterday that we could also eliminate the full 8 color-clock (4 cycle) delay by chaining 4 more 8-bit registers and clocking the luma data through them every cycle. That would make the luma output line up with the GTIA output so the programmer would not have to offset the luma plotting. Also the character modes (above) would work better. It takes 32 more flip-flops, but you said you had some 64 FF CPLDs, right?



#54 ClausB OFFLINE  

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Posted Fri Oct 30, 2009 9:00 PM

So, you want a 32 bit delay in LUMA output? 8 color clocks?

Yes. 8 color-clocks equals 4 bus cycles. So we want a byte-wide shift register of length 4, clocked by Phi2. That's in addition to the 2-byte-wide data register fed by the SRAM. In total, we'll have a byte-wide shift register of length 6. Its output is clocked by Phi2 but it has 2 inputs, what we've called the data registers. Maybe a diagram is called for:

        ---    ---    ---    ---    ---    ---   
       | 8 |->| 8 |->| 8 |->| 8 |->| 8 |->| 8 |->Mux
        ---    ---    ---    ---    ---    ---   
         ^      ^
         |      |
         |      1st SRAM read
         2nd SRAM read
The bytes shift horizontally on every Phi2 rising edge and, at the same time, the 1st byte of SRAM data clocks into the second register. 140 ns later, the 2nd byte of SRAM data clocks into the first register. Then on the next cycle, they all shift horizontally again but there are no SRAM data because it is not a DMA cycle. The next cycle is DMA so the whole process repeats.

#55 ClausB OFFLINE  

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Posted Sat Oct 31, 2009 6:16 AM

It was late and I got it a bit wrong.

        ---    ---    ---    ---    ---    ---   
       | 8 |->| 8 |->| 8 |->| 8 |->| 8 |->| 8 |->Mux
        ---    ---    ---    ---    ---    ---   
         ^
         |
         SRAM data
On the Phi2 rising edge during a DMA cycle, the 1st byte of SRAM data clocks into the 1st register. 140 ns later, all bytes shift horizontally and the 2nd byte of SRAM data clocks into the 1st register. Then on the next cycle, 140 ns after Phi2, they all shift horizontally again but there are no SRAM data because it is not a DMA cycle. The next cycle is DMA so the whole process repeats.

This sequence gives us the 8.5 color-clock delay that I measured on the prototype.

#56 ClausB OFFLINE  

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Posted Sat Oct 31, 2009 9:10 AM

I think we're ready for a first stab at some CPLD equations. I don't know CUPL but here is some pseudo-code:

Ins:
Ph2         ; Bus clock (cart pin S)
Ph2D        ; Ph2 thru 140 ns delay
Ck2D        ; Ck2 thru 70 ns delay
Data[0..7]  ; Data bus (cart pins -)
nS4         ; Pages 80-9F select, active low (cart pin 1 and SRAM enable)
RnW         ; Read not Write (cart pin R)
nD5         ; Page D5 select, active low (cart pin 15)
 
Outs:
RA16        ; SRAM upper address
RA15
RA14
RA13
nRWE        ; SRAM Write Enable, active low
Ck2         ; to 70 ns delay
Luma[0..3]  ; to video summing
 
FFs:
Mode[0..1]
Bank[0..3]
Reg0[0..7]
Reg1[0..7]
Reg2[0..7]
Reg3[0..7]
Reg4[0..7]
Reg5[0..7]
 
Combinatorial Equations:
nRWE = RnW and -Ph2
RA16 = Bank[3]
RA15 = Bank[2]
RA14 = Bank[1] or -Ph2
RA13 = Bank[0] or Ck2
Ck2 = Ph2 xor Ph2D
Stat[0] = Ck2 xnor Ck2D     ; LHLHLHLH
Stat[1] = Ck2               ; HHLLHHLL
Stat[2] = -Ph2D             ; LLHHHHLL
Luma = (Truth table function of Mode, Stat, and Reg5)
 
Sequential Equations:
On (-Ph2 and -nD5) Mode[0..1] = Data[4..5]
On (-Ph2 and -nD5) Bank[0..3] = Data[0..3]
On Ph2D Reg5 = Reg4
On Ph2D Reg4 = Reg3
On Ph2D Reg3 = Reg2
On Ph2D Reg2 = Reg1
On Ph2D Reg1 = Reg0
On Ph2D Reg0 = Data
On (Ph2 and -nS4) Reg0 = Data


#57 bob1200xl OFFLINE  

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Posted Sun Nov 1, 2009 9:23 AM

If we do not load the 'data' reg on each cycle, won't we have an unconditional blank pixel(s) in the output?

I think the best way to implement this behavior in the CPLD is to leave the data in the regs (don't shift it) and just use a pointer to gate in and out of the active register. We would need to actually move data if we were decoding the output bits accross registers or some such, but all we will do is output bits in certain sequences. This looks like a little scratch-pad memory with dual ports.

Bob



It was late and I got it a bit wrong.

        ---    ---    ---    ---    ---    ---   
       | 8 |->| 8 |->| 8 |->| 8 |->| 8 |->| 8 |->Mux
        ---    ---    ---    ---    ---    ---   
         ^
         |
         SRAM data
On the Phi2 rising edge during a DMA cycle, the 1st byte of SRAM data clocks into the 1st register. 140 ns later, all bytes shift horizontally and the 2nd byte of SRAM data clocks into the 1st register. Then on the next cycle, 140 ns after Phi2, they all shift horizontally again but there are no SRAM data because it is not a DMA cycle. The next cycle is DMA so the whole process repeats.

This sequence gives us the 8.5 color-clock delay that I measured on the prototype.



#58 ClausB OFFLINE  

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Posted Sun Nov 1, 2009 6:24 PM

If we do not load the 'data' reg on each cycle, won't we have an unconditional blank pixel(s) in the output?

No because we load it twice every other cycle. That is, we read the SRAM twice on each DMA cycle, and DMA happens every other cycle in ANTIC's highest resolution modes.

I think the best way to implement this behavior in the CPLD is to leave the data in the regs (don't shift it) and just use a pointer to gate in and out of the active register. We would need to actually move data if we were decoding the output bits accross registers or some such, but all we will do is output bits in certain sequences. This looks like a little scratch-pad memory with dual ports.

That would require 3 more FFs for a counter to address the 6 registers in turn, as well as more complex clocking and muxing logic. The shift register is simpler, no?

#59 bob1200xl OFFLINE  

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Posted Sun Nov 1, 2009 10:26 PM

From here, it may be easier to implement (and understand) the multiplexer modes if we do it all in logic rather than using shift registers. We would have six identical sets of macrocells, for example.

No matter. It usually becomes clearer as we develop the CPLD. If we get all tangled up in one approach, we'll try another.

Bob




If we do not load the 'data' reg on each cycle, won't we have an unconditional blank pixel(s) in the output?

No because we load it twice every other cycle. That is, we read the SRAM twice on each DMA cycle, and DMA happens every other cycle in ANTIC's highest resolution modes.

I think the best way to implement this behavior in the CPLD is to leave the data in the regs (don't shift it) and just use a pointer to gate in and out of the active register. We would need to actually move data if we were decoding the output bits accross registers or some such, but all we will do is output bits in certain sequences. This looks like a little scratch-pad memory with dual ports.

That would require 3 more FFs for a counter to address the 6 registers in turn, as well as more complex clocking and muxing logic. The shift register is simpler, no?



#60 warerat OFFLINE  

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Posted Tue Nov 3, 2009 3:19 PM


Yep - we could do that. Which IC were you looking at? They seem to have the ability to make the delays anything we want - that can't be a low volume project! Can it? If 70ns is a standard (low volume part) value, that should work. The duty cycle won't quite be 50% but that won't matter so much.

This is the email quote I got yesterday:

MOQ is 10 pieces
3D7323Z-70 $8.68 each 1 week to ship
MDU3C-70 $11.55 each 4-6 weeks

This is the part:
http://www.datadelay...eets/3d7323.pdf

The delay tolerance is 2%. The ideal delays are 69.8 ns for NTSC and 70.5 ns for PAL. They differ by less than the tolerance.


Would something like a IDT ICS570 work to generate the clocks?

#61 bob1200xl OFFLINE  

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Posted Tue Nov 3, 2009 5:51 PM

Looks like it would. Very cool. Cheap, too.

Bob






Yep - we could do that. Which IC were you looking at? They seem to have the ability to make the delays anything we want - that can't be a low volume project! Can it? If 70ns is a standard (low volume part) value, that should work. The duty cycle won't quite be 50% but that won't matter so much.

This is the email quote I got yesterday:

MOQ is 10 pieces
3D7323Z-70 $8.68 each 1 week to ship
MDU3C-70 $11.55 each 4-6 weeks

This is the part:
http://www.datadelay...eets/3d7323.pdf

The delay tolerance is 2%. The ideal delays are 69.8 ns for NTSC and 70.5 ns for PAL. They differ by less than the tolerance.


Would something like a IDT ICS570 work to generate the clocks?



#62 bob1200xl OFFLINE  

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Posted Tue Nov 10, 2009 2:44 PM

Attached File  cartex9.pcb.zip   24.49KB   90 downloads

OK...

I don't know about the rest of you, but I need a cartridge extender. So, here is a PCB that fits in a standard Atari cartridge (with the top sawn off) and puts all the cartridge signals on a 34 pin flat cable. There is an extender at the top where a cartridge may be inserted (with some difficulty) S4, S5, RD4, and RD5 are routed out to the flat cable and not connected to the cart connector so you can enable and disable any cartridge that you have plugged in. (that's why there are 34 pins)

That is... if this board works the way I want it to. Take a look at it using the free s/w at ExpressPCB. Tell me what you think.

Three of these boards cost $51 plus shipping. That makes six extenders.

Bob

** I had to add the extension .zip to the file - it is not a zip files, just delete the extension ***

#63 bob1200xl OFFLINE  

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Posted Tue Nov 17, 2009 3:43 PM

I have ordered some of the cartridge adaptors. I'll start the board layout so we can try some of these ideas. Do you think you have all the I/O lines defined here? That's really the first step in the CPLD.

Would it be OK if we don't negate the active low lines? I am used to S4 being active low - nS4 would be active high in my mind. Or, should I just learn a new trick?

Can you see the PCB layout, guys?

Bob



I think we're ready for a first stab at some CPLD equations. I don't know CUPL but here is some pseudo-code:

Ins:
Ph2         ; Bus clock (cart pin S)
Ph2D        ; Ph2 thru 140 ns delay
Ck2D        ; Ck2 thru 70 ns delay
Data[0..7]  ; Data bus (cart pins -)
nS4         ; Pages 80-9F select, active low (cart pin 1 and SRAM enable)
RnW         ; Read not Write (cart pin R)
nD5         ; Page D5 select, active low (cart pin 15)
 
Outs:
RA16        ; SRAM upper address
RA15
RA14
RA13
nRWE        ; SRAM Write Enable, active low
Ck2         ; to 70 ns delay
Luma[0..3]  ; to video summing
 
FFs:
Mode[0..1]
Bank[0..3]
Reg0[0..7]
Reg1[0..7]
Reg2[0..7]
Reg3[0..7]
Reg4[0..7]
Reg5[0..7]
 
Combinatorial Equations:
nRWE = RnW and -Ph2
RA16 = Bank[3]
RA15 = Bank[2]
RA14 = Bank[1] or -Ph2
RA13 = Bank[0] or Ck2
Ck2 = Ph2 xor Ph2D
Stat[0] = Ck2 xnor Ck2D     ; LHLHLHLH
Stat[1] = Ck2               ; HHLLHHLL
Stat[2] = -Ph2D             ; LLHHHHLL
Luma = (Truth table function of Mode, Stat, and Reg5)
 
Sequential Equations:
On (-Ph2 and -nD5) Mode[0..1] = Data[4..5]
On (-Ph2 and -nD5) Bank[0..3] = Data[0..3]
On Ph2D Reg5 = Reg4
On Ph2D Reg4 = Reg3
On Ph2D Reg3 = Reg2
On Ph2D Reg2 = Reg1
On Ph2D Reg1 = Reg0
On Ph2D Reg0 = Data
On (Ph2 and -nS4) Reg0 = Data



#64 warerat OFFLINE  

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Posted Tue Nov 17, 2009 8:23 PM

Would it be OK if we don't negate the active low lines? I am used to S4 being active low - nS4 would be active high in my mind. Or, should I just learn a new trick?


nS4, S4n, S4_n, S4-, S4*, and S4(with over-bar) all mean the same thing- active low signal S4. Just different notation. ;)

Edited by warerat, Tue Nov 17, 2009 8:24 PM.


#65 bob1200xl OFFLINE  

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Posted Wed Nov 18, 2009 11:07 AM

Not to me... I've been working in logic for a long time and there is no self-designated active low signal name. All those qualifiers either mean nothing or NOT(signal name). Atari doesn't even use the overbar consistently, which would be a good compromise except I have no way to type one. Thinking in logical mode just requires the signal name and asserted/not asserted. The only time we really care what polarity that represents is at the circuit level when we're doing the design. Otherwise you get things like (S4 and CLK04) being listed as (S4- NOR !CLK04) that you have to wrap your head around to make sense of. It should be perfectly clear that S4 AND CLK02 mean S4 and CLK02 are active at the same time, regardless of the actual polarities involved. (I define clocks active when high, by the way)



Bob





Would it be OK if we don't negate the active low lines? I am used to S4 being active low - nS4 would be active high in my mind. Or, should I just learn a new trick?


nS4, S4n, S4_n, S4-, S4*, and S4(with over-bar) all mean the same thing- active low signal S4. Just different notation. ;)



#66 bob1200xl OFFLINE  

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Posted Tue Nov 24, 2009 10:07 AM

Here are the cartridge adaptors that I had made for this project. They need some tweaking to be really nice but they'll work fine for development. If you mount them in an old, sawed off cartridge like I did, they fit nice and snug in a 1200XL, 600XL and a 130XE. I have four extra. If anyone wants one so they can work on the LEM, PM me.

Bob

DSC00877.JPG

#67 bob1200xl OFFLINE  

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Posted Thu Dec 3, 2009 11:04 AM

The first thing we need in CUPL is the blank form. (see LEM.PLD) It has the header, which has some required fields - particularly the DEVICE entry. This tells the compiler which chip we are using. You generate this startup file from the FILE/NEW dropdown. It will ask you for the number of INPUT pins, OUTPUT pins, and PINNODES. (pinnodes are the internal macrocells that do not connect to the Outside World as outputs) You probably don't know these quantities yet, so just put in a guess. It is easy to add or delete them later.

From here, we will enter the pin numbers of the various inputs and outputs. Which we don't know until we lay out the board.

So, S14b3.pcb is a start on the layout. It shows just the 34 pin header, memory (512Kx8) and CPLD. The header plugs into the cartridge slot through the adaptor that I made for this project. The pins at the edges are spares that carry cart selection lines back to the socket on the adaptor and should be ignored. The pin at the upper-right (SECOND one down) is cart pin 1. The upper-left is cart pin A. The lower-right (SECOND pin up) is cart 15 and lower-left is S.

The parts I do not have are the clock circuit and the video summing circuit. Anybody got an idea for video summing?

From this point in the PCB, you can get a feeling for where you can free up space. Pull everything tighter to the left seems useful. (we may not need any extra space and can just leave it all alone - depends on how much hardware we use for video and clock)

Bob


Attached File  S14b3.zip   11.98KB   81 downloads



I think we're ready for a first stab at some CPLD equations. I don't know CUPL but here is some pseudo-code:

Ins:
Ph2         ; Bus clock (cart pin S)
Ph2D        ; Ph2 thru 140 ns delay
Ck2D        ; Ck2 thru 70 ns delay
Data[0..7]  ; Data bus (cart pins -)
nS4         ; Pages 80-9F select, active low (cart pin 1 and SRAM enable)
RnW         ; Read not Write (cart pin R)
nD5         ; Page D5 select, active low (cart pin 15)
 
Outs:
RA16        ; SRAM upper address
RA15
RA14
RA13
nRWE        ; SRAM Write Enable, active low
Ck2         ; to 70 ns delay
Luma[0..3]  ; to video summing
 
FFs:
Mode[0..1]
Bank[0..3]
Reg0[0..7]
Reg1[0..7]
Reg2[0..7]
Reg3[0..7]
Reg4[0..7]
Reg5[0..7]
 
Combinatorial Equations:
nRWE = RnW and -Ph2
RA16 = Bank[3]
RA15 = Bank[2]
RA14 = Bank[1] or -Ph2
RA13 = Bank[0] or Ck2
Ck2 = Ph2 xor Ph2D
Stat[0] = Ck2 xnor Ck2D     ; LHLHLHLH
Stat[1] = Ck2               ; HHLLHHLL
Stat[2] = -Ph2D             ; LLHHHHLL
Luma = (Truth table function of Mode, Stat, and Reg5)
 
Sequential Equations:
On (-Ph2 and -nD5) Mode[0..1] = Data[4..5]
On (-Ph2 and -nD5) Bank[0..3] = Data[0..3]
On Ph2D Reg5 = Reg4
On Ph2D Reg4 = Reg3
On Ph2D Reg3 = Reg2
On Ph2D Reg2 = Reg1
On Ph2D Reg1 = Reg0
On Ph2D Reg0 = Data
On (Ph2 and -nS4) Reg0 = Data



#68 ClausB OFFLINE  

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Posted Sat Dec 5, 2009 8:41 AM

Sorry, I've been too busy to work on this lately. My FIRST Lego League team won the November tourney and are going to state next weekend. Unless they win again, I'll have time after that, especially over the holidays.

The first thing we need in CUPL is the blank form. (see LEM.PLD) It has the header, which has some required fields - particularly the DEVICE entry. This tells the compiler which chip we are using. You generate this startup file from the FILE/NEW dropdown. It will ask you for the number of INPUT pins, OUTPUT pins, and PINNODES. (pinnodes are the internal macrocells that do not connect to the Outside World as outputs) You probably don't know these quantities yet, so just put in a guess. It is easy to add or delete them later.

From here, we will enter the pin numbers of the various inputs and outputs. Which we don't know until we lay out the board.

Thanks for the primer. I'll study CUPL some more and flesh this out.

So, S14b3.pcb is a start on the layout. It shows just the 34 pin header, memory (512Kx8) and CPLD. The header plugs into the cartridge slot through the adaptor that I made for this project. The pins at the edges are spares that carry cart selection lines back to the socket on the adaptor and should be ignored. The pin at the upper-right (SECOND one down) is cart pin 1. The upper-left is cart pin A. The lower-right (SECOND pin up) is cart 15 and lower-left is S.

The parts I do not have are the clock circuit and the video summing circuit. Anybody got an idea for video summing?

As above, the clock circuit could be simple delay lines. If we add a clock gen chip then most of those sequential equations will change, and I think they'll be more complicated. If you layout the delay line IC described above, then we could solder in RC circuits for the first test boards, before we commit to buying the ICs.

As for the video summing, I still plan to experiment with the prototype to see if the simple resistor ladder and diode circuit works well.

#69 bob1200xl OFFLINE  

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Posted Sun Dec 6, 2009 9:01 PM

I have filled in the I/O pins that we know about. The pin assignment also takes care of the active level for the signal - a ! denotes NOT, so !S4 means S4 is active at a zero level. In the equations and such, all you will see is S4 that denotes S4 Active. (even thogh it's a zero level in the hardware) !S4 in the equations section means S4 is Not Active - OK?

MAxx are the addresses going to the memory chip from the CPLD. Axx would be an address from the cart socket. MCS is MemoryChipSelect and MWE is MemoryWriteEnable. I tried to keep all the Atari signal names the same as we see them in the Atari documentation.

The field to the right of each line is a comment field. Good thing to have if you're going to make something complex.

Name LEM ;
PartNo 00 ;
Date 11/29/2009 ;
Revision 01 ;
Designer Claus B. ;
Company Atari Rulz!! ;
Assembly None ;
Location ;
Device f1504plcc44 ;

/* *************** INPUT PINS *********************/
PIN 06 = !S4 ; /* */
PIN 11 = D4 ; /* */
PIN 12 = D5 ; /* */
PIN 13 = D2 ; /* */
PIN 14 = D1 ; /* */
PIN 16 = D3 ; /* */
PIN 17 = D7 ; /* */
PIN 18 = D0 ; /* */
PIN 20 = !S5 ; /* */
PIN 21 = D6 ; /* */
PIN 25 = R/W ; /* */
PIN 26 = !CCTL ; /* */
PIN 27 = B02 ; /* */
PIN = ; /* */
PIN = ; /* */
PIN = ; /* */
PIN = ; /* */
PIN = ; /* */
PIN = ; /* */

/* *************** OUTPUT PINS *********************/
PIN 04 = MA7 ; /* */
PIN 05 = MA12 ; /* */
PIN 07 = MA17 ; /* */
PIN 08 = RD4 ; /* */
PIN 09 = !MWE ; /* */
PIN 19 = !MCS ; /* */
PIN 24 = RD5 ; /* */
PIN 39 = MA18 ; /* */
PIN 40 = MA16 ; /* */
PIN 41 = MA14 ; /* */
PIN = ; /* */
PIN = ; /* */
PIN = ; /* */
PIN = ; /* */
PIN = ; /* */

/* *************** PINNODES *********************/
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */
PINNODE = ; /* */


Bob

#70 ClausB OFFLINE  

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Posted Mon Dec 7, 2009 8:37 PM

Can CUPL group together similar signals? For example, can we define D[0] thru D[7] and then refer to the whole data bus byte as D or D[0..7] in the equations (as I did in the pseudocode)?

#71 bob1200xl OFFLINE  

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Posted Tue Dec 8, 2009 10:36 AM

Oh, you betcha. There are a ton of assignments and logical processes that have special handling. To define D0-D7, you enter [D0..D7]. I don't belive that you can refer to that group as 'D', however. I read the book a lot when I do this stuff and I tend to stick with what I know. I know you can define State Machines but I haven't tried them yet, as an example.


Bob




Can CUPL group together similar signals? For example, can we define D[0] thru D[7] and then refer to the whole data bus byte as D or D[0..7] in the equations (as I did in the pseudocode)?



#72 Philsan OFFLINE  

Philsan

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Posted Tue Dec 8, 2009 4:49 PM

Sorry, I've been too busy to work on this lately. My FIRST Lego League team won the November tourney and are going to state next weekend. Unless they win again, I'll have time after that, especially over the holidays.

Congratulations!

#73 ClausB OFFLINE  

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Posted Fri Dec 11, 2009 2:17 PM

I have filled in the I/O pins that we know about. The pin assignment also takes care of the active level for the signal - a ! denotes NOT, so !S4 means S4 is active at a zero level. In the equations and such, all you will see is S4 that denotes S4 Active. (even thogh it's a zero level in the hardware) !S4 in the equations section means S4 is Not Active - OK?

MAxx are the addresses going to the memory chip from the CPLD. Axx would be an address from the cart socket. MCS is MemoryChipSelect and MWE is MemoryWriteEnable. I tried to keep all the Atari signal names the same as we see them in the Atari documentation.

The field to the right of each line is a comment field. Good thing to have if you're going to make something complex.


OK. So, combining my pseudocode with your syntax gives us:

Name     LEM ;
PartNo   00 ;
Date     12/11/2009 ;
Revision 01 ;
Designer Claus B. & Bob W.;
Company  Atari Rulz!! ;
Assembly None ;
Location  ;
Device   f1504plcc44 ;

/* *************** INPUT PINS *********************/
PIN  06 = !S4                     ; /* Pages 80-9F select, active low (cart pin 1 and SRAM enable) */ 
PIN  11 = D4                      ; /* Data bus                        */ 
PIN  12 = D5                      ; /*                                 */ 
PIN  13 = D2                      ; /*                                 */ 
PIN  14 = D1                      ; /*                                 */ 
PIN  16 = D3                      ; /*                                 */ 
PIN  17 = D7                      ; /*                                 */ 
PIN  18 = D0                      ; /*                                 */ 
PIN  21 = D6                      ; /*                                 */ 
PIN  25 = R/W                     ; /* Read not Write (cart pin R)     */ 
PIN  26 = !CCTL                   ; /* Page D5 select, active low (cart pin 15) */ 
PIN  27 = B02                     ; /* Bus clock (cart pin S)          */ 
PIN  ?? = B02D                    ; /* Bus clock thru 140 ns delay     */ 
PIN  ?? = C02D                    ; /* Doubled clock thru 70 ns delay  */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 

/* *************** OUTPUT PINS *********************/
PIN  ?? = MA13                    ; /* SRAM upper address              */ 
PIN  ?? = MA14                    ; /*                                 */ 
PIN  ?? = MA15                    ; /*                                 */ 
PIN  ?? = MA16                    ; /*                                 */ 
PIN  09 = !MWE                    ; /* SRAM Write Enable, active low   */ 
PIN  ?? = C02                     ; /* Doubled clock to 70 ns delay    */ 
PIN  ?? = LUM0                    ; /* Luma outputs                    */ 
PIN  ?? = LUM1                    ; /*                                 */ 
PIN  ?? = LUM2                    ; /*                                 */ 
PIN  ?? = LUM3                    ; /*                                 */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 
PIN     =                         ; /*                                 */ 

/* *************** PINNODES    *********************/
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 
PINNODE     =                      ; /*                                 */ 

Note that we don't need S5 and RD5 because the banked SRAM will occupy pages $80 - $9F. We also don't need RD4 because the SRAM will always be active in that region of RAM, so RD4 should be tied high on the PCB. For the same reason, we don't need to generate MCS because the SRAM CS can be tied to S4 on the PCB.

#74 ClausB OFFLINE  

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Posted Sun Dec 13, 2009 9:34 AM

And here's the stage 2 diagram:

LEMs2.GIF

#75 ClausB OFFLINE  

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Posted Wed Dec 16, 2009 5:03 PM


My FIRST Lego League team won the November tourney and are going to state next weekend.

Congratulations!

Thanks! They took 8th place out of 48 in the state tourney last weekend. They rock.




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