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Number of DMA clock cycles per scanline?


Robert M

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It was you as I recall that mentioned there being 227 PAL color clocks per scanline (which, as I stated in the previous post, corresponds precisely to 454 MARIA clocks). How the external PAL clock of 4.43 MHz affects things, again, I have no clue, since I don't have any PAL hardware or any way of measuring any of this stuff.

On an NTSC 7800 a single 14.3181818MHz (4x NTSC colorburst) crystal is used to generate both the MARIA (and thereby the pixel and CPU/TIA) clocks. The color output is this clock divided by 4 and hue/phase via a tapped delay line (same as the TIA in the 2600). However, the PAL 7800 uses a separate 4.433MHz PAL colorburst crystal to generate the color output. TVs are relatively tolerant of variations in signal timing, but not in colorburst frequency or phase (especially PAL). Curiously the schematics for both the NTSC and PAL 7800s have a 14.31818MHz crystal, which is different than the 14.1875MHz measured by nichtsnutz. It would be interesting if someone could open a PAL 7800 and see if they can read the frequency off the crystal.

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  • 1 year later...

Hey, that MARIA manual is pretty neat that was posted:

http://www.atarimuseum.com/ahs_archives/archives/pdf/videogames/7800/gcc1702b_maria_specs.pdf

 

As I'm not a hardware guy, does the manual hint at any details of what is happening while DMA is starting up / shutting down?

Is it copying stuff to the screen via its own internal logic, or is it dependent on the 6502 at all?

 

I'm really curious from start to finish what's happening when DMA is called while important gamecalc-type instructions are mid-processing.

Does it just shut down things with a HALT, and then come back to them, leaving everything as it was? If so, what is really happening on the hardware side?

 

-John

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Maria screen fetches are autonomous, ie once you've set up valid Display Lists, zones etc then it goes about it's business with little/no intervention required.

 

DMA uses /Halt as per the computer line (same Sally 6502 CPU) to keep the 6502 off the bus when required.

 

Maria has 2 scanline buffers, the "next" scanline is built up while the "current" one is displayed. The programming docs give a good idea of what happens and # of cycles involved.

 

For a cluttered display, you may as well assume the 6502 loses most of the cycles on a scanline. Display Lists IIRC are re-read each scanline. Priority is a simple case of "last in, on top". Collision detection isn't done by hardware, it's up to software to take care of that, ie usually bounding box method.

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  • 8 years later...
On 6/15/2010 at 10:12 AM, GroovyBee said:

DMA startup takes between 5 and 12 cycles - so assume 12 worst case.

DMA shutdown takes between 9 to 23 cycles - so assume 23 worst case.

 

=452-12-23 MARIA cycles.

=417 MARIA cycles.

 

On 6/16/2010 at 11:02 PM, gdement said:

I had a more pessimistic calculation in my notes. I still think this looks correct according to the Maria spec, but I'd love to be wrong:

 

So DMA startup occurs at cycle 34, and consumes up to 12 cycles, giving a worst case start time of cycle 46.

DMA is aborted to begin shutdown at cycle 413.

413-46= 367 usable cycles.

 

I haven't experimented with it though.

 

On 6/17/2010 at 3:29 AM, GroovyBee said:

I don't think you are correct. Using your figures it wouldn't be possible for MARIA to handle a full screen width of 160B indirect in 2 char width mode and a sprite on top (which I know is possible).

 

e.g. For the background alone using 2 of the 5 byte headers.

 

=(2x10)+(40x(3+(2x3)) MARIA cycles.

=380 MARIA cycles.

BUMP.

 

Did anybody, in the past decade, ever figure this out?

 

gdement referenced the GCC spec: “Regular DMA is initiated on the leading edge of HBlank.” He took that to mean MARIA cycle 34. But the screen layout diagram in that document shows another HBlank, starting at cycle 440 of the previous line. I suspect that is when DMA starts.

 

I think GroovyBee’s numbers are also off, because only shutdown can happen in the 27 cycles of (right side) border. If you have 12 cycles of startup starting at 440, that leaves 413 cycles until abort.

 

Thanks to RevEng’s clarifications in the Updated Software Guide, we now understand that at least some of the variance in startup and shutdown time is based on whether SALLY is accessing the bus and if so, whether that access is throttled for TIA or RIOT. It’s tough to do something interesting without accessing the bus, and very difficult to control which MARIA cycle it lands on, but it is feasible to prevent TIA/RIOT accesses during DMA, so we can save a couple of cycles there.

 

So my read is that we reliably have 413 cycles per line for reading headers, maps, and graphics, but if we can avoid TIA and RIOT, that becomes 415.

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My ballpark calculation is to start with a full line is 454 maria cycles in length, and subtract out all of the time DMA can't be processing your DL objects. It doesn't matter where the dma starts exactly, as we can just assume it starts at the same position each time.

 

So take that absolute maximum of 454 cycles, and subtract the 28 cycles that maria allows the 6502 to run prior to dma, and then further subtract normal dma startup+shutdown penalties. (16=other line, 24=last line. we'll disregard interrupts, which are another kettle of fish). That gives you 410=last line, and 402=other line.

 

I believe the only factor not taken into account here is the dma startup and shutdown clock alignments. i.e. maria delaying the 6502 halt/resume to ensure the generated 6502 clock is at a non-fractional position. I now believe the long instructions and riot access, etc., only take away from DMA in this way, since Maria doesn't wait for a 6502 instruction to complete before halting. So for worst case numbers, you can drop another 6 maria cycles (3 for dma start, 3 for dma end) from the above totals.

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5 hours ago, playsoft said:

A quick question if anyone knows as it's just out of interest, but if graphics data is placed in RAM does Maria still require 3 cycles per byte or will it use 2 like the DLLs?

 

I believe so. The pinout doesn’t show any line to indicate valid data, and MARIA doesn’t know which addresses are RAM and which are ROM. I think it just assumes that DLs and the DLL will be available 2 cycles later, and graphics data by 3.

 

Conversely DLs and the DLL are not really required to be in RAM, they just must return in 2 cycles. In 1983 that effectively meant RAM, nowadays maybe not.

 

I haven’t tested any of this though.

 

It’s unfortunate for 7ix, where most of the graphics are in RAM. But I think I’ll be okay on DMA time anyway.

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On 10/20/2020 at 4:51 PM, bizarrostormy said:

I believe so. The pinout doesn’t show any line to indicate valid data, and MARIA doesn’t know which addresses are RAM and which are ROM. I think it just assumes that DLs and the DLL will be available 2 cycles later, and graphics data by 3.

 

Conversely DLs and the DLL are not really required to be in RAM, they just must return in 2 cycles. In 1983 that effectively meant RAM, nowadays maybe not.

 

I haven’t tested any of this though.

 

It’s unfortunate for 7ix, where most of the graphics are in RAM. But I think I’ll be okay on DMA time anyway.

 

On 10/21/2020 at 3:57 PM, TailChao said:

Maria's timing is fixed based upon the type of data being fetched, not where it's being fetched from.

Yes that makes sense, thanks.

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