18 replies to this topic

[Bryan]

Not sure if it's been posted here yet... The simulator can be run in your browser. They're also taking submissions for other IC's to model.

http://www.visual6502.org/

[Bryan]

No replies? I thought this was pretty exciting. They're working on TIA as well.

[bged]

I think it's fantastic!  Having deprocessed and photographed the CPU, they captured the layout, computed the netlist, and can simulate phase-by-phase.  Including undocumented behaviour and some surprises.  The test was to view Atari game graphics - see the big pdf file!

Being a chip person, I really like exploring the layout and seeing how it ticks.

Here's a screenshot:

[MitchSchaft]

I really wish I understood how this stuff works.

[Bryan]

MitchSchaft, on Sat Sep 18, 2010 5:19 PM, said:

I really wish I understood how this stuff works.

The principles of digital logic are actually pretty simple, it's just that it gets confusing when you build a giant circuit out of them.

[Keatah]

Bryan, on Thu Sep 16, 2010 5:17 AM, said:

Not sure if it's been posted here yet... The simulator can be run in your browser. They're also taking submissions for other IC's to model.

http://www.visual6502.org/

Ahh yes, I was occasionally looking fr this off and on a while back! Thanks!

[MitchSchaft]

Bryan, on Sat Sep 18, 2010 6:59 PM, said:

The principles of digital logic are actually pretty simple, it's just that it gets confusing when you build a giant circuit out of them.

Right. I understand 1's and 0's, I just can't imagine it when it comes to anything bigger than 1's and 0's, lol. I would love to have the visual in my head.

[SeaGtGruff]

Bryan, on Thu Sep 16, 2010 5:17 AM, said:

http://www.visual6502.org/

I can't get it to load in either IE8 or Firefox-- and yes, I *do* have active scripting enabled. I'm updating to Firefox 3.6.10 now to see if that helps. (I thought I had the latest version of Firefox, but I see I've got 3.5.11!) Has anyone else had problems getting it to load?

Michael

[SeaGtGruff]

Updated to Firefox 3.6.10, still nothing loads. The Firefox error console says "console is not defined" in line 118 of the javascript.

Michael

[SeaGtGruff]

After Googling for information about the "console is not defined" error, I concluded (rightly or wrongly) that I needed to install the Firebug add-on for Firefox. And *then* I had to start Firebug and enable the console. Now it's working. Maybe it's just me, but I think if something is required to make a web site run correctly, putting a message on the web site telling people they need to have such-and-such installed would be a lot more helpful than a message saying "try another browser."

Michael

[batari]

Interesting - I had the same problem as you, and also tracked down the issue to the firebug console and got it working.

The first thing I did was do a JAM opcode and it seems to do nothing but jump to FFFE/FFFF and stay there.

I also tried the opcodes considered unstable (ANE, LXA) and found LXA stable, and ANE to operate differently than documented on a C-64.  This suggests that even though this claims to be a full simulation, perhaps it's not considering something (such as wire delay for race conditions that could go either way in real hardware, or effects of a floating bus.)

I plan to try some of the other weird opcodes and see what happens - also I may try to see what areas go active during these opcodes and compare with some of the neighboring valid opcodes as undocumented opcodes are usually a case of several valid opcodes being decoded and executed at the same time.

[SeaGtGruff]

batari, on Sun Sep 19, 2010 1:29 AM, said:

The first thing I did was do a JAM opcode and it seems to do nothing but jump to FFFE/FFFF and stay there.

I also tried the opcodes considered unstable (ANE, LXA) and found LXA stable, and ANE to operate differently than documented on a C-64.  This suggests that even though this claims to be a full simulation, perhaps it's not considering something (such as wire delay for race conditions that could go either way in real hardware, or effects of a floating bus.)

I plan to try some of the other weird opcodes and see what happens - also I may try to see what areas go active during these opcodes and compare with some of the neighboring valid opcodes as undocumented opcodes are usually a case of several valid opcodes being decoded and executed at the same time.

I haven't tried typing in a program to see how it works, and I wish there were a way to load a .bin into the RAM area, or at least type a short program into a text box using assembler opcodes. On the other hand, it's probably more useful to just type in a few instructions so you can watch what happens as they execute.

It will be interesting to see the TIA simulator in action, but I wonder how they'll implement it as far as the display is concerned? The main page says the TIA simulator is finished, but there's no page for it yet, so maybe they're still trying to work that out. For example, will there be a TV screen so we can watch the output being drawn, or will it just be the chip in action? And will a 6507(?) be shown alongside the TIA so we can see them interacting? Then there's the 6532 RIOT simulator that they're working on as well. It would be very cool if all three chips could be seen interacting, and possibly have console switches and input devices as well.

Regarding the Firebug bug, I'm wondering if they even realized it would be a problem? If they're programming in Javascript, and presumably have Firebug installed, they might not have considered that the bug would occur if Firebug isn't installed and the console enabled. To be honest, the main reason it irked me to the extent it did was their suggestion to try another browser, which came across as IE-bashing. "If this page doesn't work for you, it must be your browser, so ditch IE and get a *real* browser!" It would be ideal if the simulators worked in *all* browsers, because a lot of people do use IE, and they might get frustrated if they tried downloading and installing another browser, only to discover that the page *still* wouldn't load correctly. But I guess anyone who would be interested in the simulations in the first place would have to be a geek anyway, and would presumably have the smarts needed to figure out what the problem is and resolve it. Unfortunately for me, I'm not *that* big of a geek, and my smarts leave a lot to be desired, so it's a wonder I was able to figure out how to resolve the issue myself!

Michael

[Bryan]

batari, on Sun Sep 19, 2010 1:29 AM, said:

(such as wire delay for race conditions that could go either way in real hardware, or effects of a floating bus.)

That's kinda what I was thinking. I'm sure the simulator isn't dealing with any routing delay or unusual precharge effects, but rather updates all nodes on the clock (which should show all intended behavior). Fortunately, just being able to see how the innards are connected will give us the best insight into any remaining side-effects.

[supercat]

batari, on Sun Sep 19, 2010 1:29 AM, said:

I also tried the opcodes considered unstable (ANE, LXA) and found LXA stable, and ANE to operate differently than documented on a C-64.  This suggests that even though this claims to be a full simulation, perhaps it's not considering something (such as wire delay for race conditions that could go either way in real hardware, or effects of a floating bus.)

My guess as to what ANE is doing, without seeing a transistor-level simulation, is that on one internal bus the 6507 is outputting the value read from the accumulator, and on another bus the 6507 is outputting the value of the first bus and the value read from the data bus.  If the second bus has inverted logic levels compared with the first, the effect would be a race condition, since both buses would be precharged to '1', and once either bus was pulled low the system would become stable.  I wonder it that's what's actually happening?

[Bryan]

It would be nice to verify/improve this diagram now that the simulation is available. It shows how the various busses (Data bus, Special bus, AdrH/L bus) can be connected together via the pass transistors.

Attached Thumbnails

• 

Edited by Bryan, Sun Sep 19, 2010 7:29 PM.

[bged]

SeaGtGruff, on Sat Sep 18, 2010 11:12 PM, said:

Updated to Firefox 3.6.10, still nothing loads. The Firefox error console says "console is not defined" in line 118 of the javascript.

Michael

Oops - fixed that!  (I'm acting as a co-maintainer, recently joined the team and not taking credit for the past year of work...)

Bryan said:

It would be nice to verify/improve this diagram now that the simulation is available

Agreed!  The overall aim of the project is as an educational/investigative resource. Now we have all the activity on the busses and latches, we have the info we need to annotate such a diagram. In due course we hope to construct an accurate schematic, and then we can verify or fix the block diagram. With luck, we'll get lots of help from interested people - there will be a forum, and so on.

Cheers
Ed

[bged]

batari, on Sun Sep 19, 2010 1:29 AM, said:

The first thing I did was do a JAM opcode and it seems to do nothing but jump to FFFE/FFFF and stay there.

That's what we expect, I think?  What we can now do is understand exactly why: which states the Timing Control goes through, and why interrupts won't get a look in.

[supercat]

bged, on Mon Sep 20, 2010 2:28 PM, said:

Agreed!  The overall aim of the project is as an educational/investigative resource. Now we have all the activity on the busses and latches, we have the info we need to annotate such a diagram. In due course we hope to construct an accurate schematic, and then we can verify or fix the block diagram. With luck, we'll get lots of help from interested people - there will be a forum, and so on.

I was looking at the thing briefly yesterday; I like the idea a lot, but would like it even better if it were annotated.  One thing I'd be curious about is what would happen if each phase were subdivided into two sub-phases and used three-state ('0','1','X') logic thus: In the first sub-phase, any node which is, or may be, pulled to a value other than its current value, is assigned a value of 'X'; simulation iterates in that state until all nodes that are going to be assigned 'X' have been.  In the second sub-phase, nodes whose state can be determined to be '0' or '1' would be resolved.  This would mean that any node whose result was affected by a race condition would report a value of "X", even if in hardware one state would be guaranteed to "win".  My guess would be that ANE (the non-working "LAX #imm") would load the accumulator with all "X"'s, but most opcodes wouldn't.  Not sure about "JAM".

[Bryan]

I'd like to send them a full A8 chipset as soon as I get more of my stuff unpacked.