So N is 4..6.
And another thing again...:
The cycles, be sure your instructions need more cycles than 3
and less than 7, otherwise no value will be stored.
Thanks for the reply! Yeah I saw this document, but I'm still wondering how the Supercharger "knows" what cycle is the one that makes it store the data.
There's two possible ways I can see it doing this:
* Counting CPU cycles by watching address line transitions after the read of F000-F0FF
* Looking for an "out of order" address to be accessed, within N cycles of the read to F000-F0FF
The problem with the first, is if you do not specifically read from where you wish to write at the proper cycle, it will over-write the code that's executing. Not a huge problem- the code's never supposed to do this.
The second one would watch the address lines. During execution, they should continuously increment as code runs. Within N cycles (3-7) of the read of F0xx, and an out of order access, write to the RAM. This has another problem, but I don't think it is an issue. The problem being that you cannot overwrite the next byte of memory, but I'm pretty sure this isn't an issue. Even with self modifying code it's not going to be a problem, because you don't usually write to the next location you're going to execute.
Thinking from a hardware standpoint, it's a tossup as to which is easier to implement on silicon, though the former might be a bit easier.
In either case, it's the Supercharger chip that actually performs the memory write, which I find highly amusing. It has to stuff data onto the bus and hit /WE on the RAM chips during the read cycle to turn it into a write cycle.