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How do I read a Pinout with Memory info?

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#1 esplonky OFFLINE  



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Posted Fri Apr 13, 2012 9:16 AM

I've seen pinouts of the 6507 and the 6502 pinouts and they all have memory info and I want to know how to read a pinout.

#2 SeaGtGruff OFFLINE  



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Posted Fri Apr 13, 2012 11:40 PM

I've seen pinouts of the 6507 and the 6502 pinouts and they all have memory info and I want to know how to read a pinout.

I'm not sure what you mean-- can you elaborate?

As I understand it, a "pinout" is just a diagram or list that shows what the pins or lines are on a chip and what they're used for. An example of a 6502 pinout is shown below. I drew it myself in Paint, using many essentially identical pinouts from different sources-- the only real differences between them being the precise way the pins are labeled (such as "AB0" versus "A0," or other minor differences like that).


In this style of pinout, the rectangle represents the chip. It's common to draw a semicircle cut out of the top edge of the rectangle, but I guess I didn't draw one.

The numbers inside the rectangle are the pin numbers (1 through 40).

The labels outside the rectangle beside each pin show what the pins are used for. Some pins are used for input, some are used for output, and some are used for both ("bidirectional"). I added the arrows later, which is why the pins for the clock signals say "(IN)" and "(OUT)" but then also have arrows. An arrow that points toward the chip indicates that the pin is used for an input line. An arrow that points away from the chip indicates that the pin is used for an output line. An arrow that points in both directions indicates that the pin is used for both input and output.

Pin 1 and pin 21 are both labeled "Vss" (sometimes labeled as "GND"), which indicates that those two pins/lines are connected to ground.

Pin 8 is labeled "Vcc" (sometimes labeled as a voltage), which indicates that the pin/line is connected to a power source.

Pins 3, 37, and 39 are labeled with a circle with a vertical line through it, or the Greek letter "phi" (sometimes labeled "CLK" or something similar). These are the pins/lines that are used for the clock signals. The numbers beside the "phi" symbol indicate the clock phase.

The clock 0 line (pin 37) is used to feed a "phase 0" clock signal from an outside source (either directly from an oscillator circuit, or from another chip like the TIA) into the 6502. A clock signal is an alternating high/low voltage signal that defines the clock cycle, and thus the speed at which the 6502 runs. Generally speaking a clock signal is low 50% of the time and high 50% of the time, and a complete clock cycle contains both a low and a high period. The clock 0 cycle is "low-high" (the clock 0 signal is low for the first half of the cycle and high for the second half).

The clock 1 line (pin 3) and clock 2 line (pin 39) are used to send the "phase 1" and "phase 2" clock signals from the 6502 to other chips or devices. The 6502 takes the clock 0 signal that it gets from outside and uses it to generate the clock 1 and clock 2 signals, which tell other chips or devices when it's safe to read from or write to the 6502. The clock 1 signal is basically an inversion of the clock 0 signal (high first, then low), but is slightly delayed due to the process required to generate it. They also differ in that the clock 1 signal's low period is slightly longer than its high period. The clock 2 signal is almost exactly identical to the clock 0 signal-- or the inversion of the clock 1 signal-- so its low period comes first, but it's slightly delayed from clock 0 just like clock 1 is, and its low period is also slightly longer than its high period. This ensures that clock 1 and clock 2 will never both be high at the same time. So a complete clock cycle is "phase 1" (clock 1 high) then "phase 2" (clock 2 high). When clock 1 is high it tells other chips or devices that they can read from the 6502's address bus or data bus. When clock 2 is high it tells other chips or devices that they can write to the 6502's data bus.

Pins 9 through 20, and pins 22 through 25 are used for the 16-bit address bus, and their labels indicate which address bits they transmit. Thus, "A0" (or "AB0") transmits bit 0 of the address, whereas "A8" (or "AB8") transmits bit 8 of the address. Since each bit can be on or off (1 or 0, high or low) and there are 16 bits (numbered 0 through 15), the 6502 can recognize 65536 different addresses (or 64K of memory locations)-- that is, 2 to the 15th power. The address lines are output-only, so the 6502 can send addresses to other chips and devices, but they can't send addresses back to the 6502 using the address lines (or address bus). Instead, they must send addresses to the 6502 by using the data lines (or data bus).

Pins 26 through 33 are used for the 8-bit data bus, and their labels indicate which data bits they transmit. Thus, "D0" (or "DB0") transmits bit 0 of the data, whereas "D4" (or "DB4") transmits bit 4 of the data. There are 8 lines or bits, so the data are 1 byte is size and can have 256 values (0 to 255)-- that is, 2 to the 7th power. The data lines are bidirectional-- they can send data from the 6502 to other chips or devices, or receive data from them. If another chip or device needs to send an address to the 6502, it must send the low byte first (bits 0 through 7 of the address) followed by they high byte (bits 8 through 15 of the address).

Pin 34 is used for the "R/W" or "read-write" line. This line tells other chips or devices whether the 6502 is reading from them or writing to them. Since this is determined by the type of instruction that the 6502 is executing, R/W is an output-only line. That is, the 6502 can tell other chips or devices that it's reading from them or writing to them, but the other chips or devices can't tell the 6502 that they want to read from it or write to it. In my pinout I drew a bar over the W, but often the bar is not shown. When a bar is over a label it means that the line is considered to be "active-low," or "on" when its voltage is low. Thus, when the R/W line is high it indicates that the 6502 is reading data from the data bus, and when it's low it indicates that the 6502 is writing data to the data bus. Since most fonts don't include the ability to draw a bar over a character, it's common to use a / or ~ in place of the bar. Thus, "/W" or "~W" is the same as drawing a bar over the W to indicate that the "write" signal is active-low.

Pin 2 is used for the "RDY" or "ready" line, which can pause or restart the 6502. Normally the 6502 is constantly executing instructions. When the RDY line goes from high to low it causes the 6502 to stop after finishing its current instruction and pause for as long as the RDY line remains low. Then when the RDY line goes from low to high it causes the 6502 to resume processing instructions. This allows other chips or devices to tell the 6502 to wait until they're ready for it to continue with the next instruction. For example, the Atari 2600 sets the RDY line low (thus pausing the 6507) when you write to the TIA's WSYNC register, and sets the RDY line high again (thus telling the 6507 to resume processing) when the horizontal blank begins.

Pin 7 is used for the "SYNC" line, which identifies whether or not the 6502 is fetching the "op codes" for an instruction-- SYNC is high while the op code/s is/are being fetched, and goes low again when the 6502 has finished fetching the op code/s.

Pin 38 is used for the "/S.O." (or "/SO") or "set overflow flag" line, which is an input line. The bar over the label indicates that the /SO line is active-low. When /SO goes from high to low, it causes the 6502 to set (turn on) the overflow flag in the 6502's "processer status register."

Pins 4, 6, and 40 are used for the "/IRQ," "/NMI," and "/RES" lines, respectively. These active-low input lines receive "interrupt" signals from other chips or devices, causing the 6502 to interrupt whatever it's doing and perform a special "interrupt routine." As noted earlier, the 6502 can recognize 65536 different addresses, and 6 of these addresses are designated as being 3 "interrupt vectors." Each vector is a 2-byte address that tells the 6502 where a particular interrupt routine is located in memory.

The IRQ vector is in addresses $FFFE (low byte) and $FFFF (high byte). When the /IRQ line goes from high to low, it causes the 6502 to interrupt the normal program flow, push the next address and the current processor status onto the stack, and load the data at addresses $FFFE and $FFFF into the program counter. Then the 6502 starts executing the code found at the new address and continues until an "RTI" or "return from interrupt" instruction is encountered. Then it retrieves the previous processor status and program counter values from the stack and goes back to wherever it was in the code before the interrupt occurred. An IRQ interrupt is a "maskable interrupt," meaning it can be disabled by setting (turning on) the interrupt flag in the processor status register.

The NMI vector is in addresses $FFFA (low byte) and $FFFB (high byte). When the /NMI line goes from high to low, it causes the 6502 to jump to the address pointed to by $FFFA and $FFFB, just like what happens when an IRQ interrupt occurs. "NMI" means "non-maskable interrupt," and NMI interrupts can't be disabled by setting the 6502's interrupt flag.

The RES vector is in addresses $FFFC (low byte) and $FFFD (high byte). When the /RES line goes from high to low, it causes the 6502 to stop and inhibit all read/write activity. When the /RES line goes high again, it triggers the 6502 to "reset" itself by performing a "power-up" initialization sequence, then it loads the address contained in the RES (or RESET) vector and starts executing the program from that point. Thus, the RESET vector in $FFFC and $FFFD must always point to the code you want your program to execute first, at power-up.

Pins 5, 35, and 36 are labeled "N.C." (or "NC"), meaning "no connection" or "not connected." This indicates they aren't connected to anything inside the 6502-- they're provided for future expansion (and some variations of the 6502 do use one or more of these pins).

The pinout for the 6507 is shown below:


As you can see, there are only 28 pins-- 12 pins fewer than the 6502 has. That means some of the pins found on the 6502 are missing from the 6507-- in particular, one of the Vss lines, the clock 1 line, bits 13 through 15 of the address bus, the SYNC line, the /SO line, the /IRQ line, the /NMI line, and the 3 NC lines.

The most significant impact of these missing lines are that the 6507 can access only 8192 different addresses (or 8K of memory)-- that is, 2 to the 12th power. The 6507's internal address bus still has 16 bits, and all 16 bits of the address bus can be set by reading the data bus (low byte first, then high byte), but the 6507 can't send the upper 3 bits of the address to other chips or devices, so it can access only the first 8K of the full 64K memory space. For example, the program can tell the 6507 to read data from address $FABC, but when the 6507 tries to send address $FABC to the other chips or devices it will actually send address $1ABC to them.

Another significant difference between the 6502 and the 6507 is that the 6507 has no way to receive IRQ or NMI interrupt requests. But it's still possible to make the 6507 interrupt itself and go perform the code that's pointed to by the IRQ vector, because the "BRK" (or "break") instruction forces the 6502 or 6507 to perform a non-maskable interrupt-- but using the IRQ vector rather than the NMI vector. It should be noted that after the 6502 or 6507 returns from an interrupt that was triggered by a BRK instruction, execution will resume 2 bytes *after* the BRK instruction-- that is, the byte immediately following the BRK instruction will be skipped.

We can look at the pinouts for the TIA and RIOT next, but this should be plenty to chew on for now-- especially since I'm not sure whether you really mean a "pinout" as shown in this post, or perhaps you meant a "schematic" instead.

#3 SpiceWare ONLINE  



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Posted Sat Apr 14, 2012 10:14 AM

Nice! I knew what a lot of the pins meant, but not all.

Your 2 to the power statements are off by 1:
256 = 2^8
8192 = 2^13
65536 = 2^16

It's a common mistake to be off by one because the counts start at 0 instead of 1:
8 data lines labeled 0-7
13 address lines labeled 0-12
16 address lines labeled 0-15

Edited by SpiceWare, Sat Apr 14, 2012 10:16 AM.

#4 Wickeycolumbus OFFLINE  


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Posted Sat Apr 14, 2012 11:07 AM

Definitely a great post SeaGtGruff :thumbsup:

#5 SeaGtGruff OFFLINE  



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Posted Sat Apr 14, 2012 11:55 AM

Your 2 to the power statements are off by 1:

Crud, you're right! I actually wrote 16th power and 8th power first, but then I went back and changed them before I posted-- I was thinking, "Wait, bit 0 has a value of 1 because 2 to the 0th power is 1," and I confused myself (not an uncommon occurrence).

#6 esplonky OFFLINE  



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Posted Sat Apr 14, 2012 4:05 PM

You are awesome SeaGtGruff!!! Thanks A Bunch!

#7 SeaGtGruff OFFLINE  



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Posted Sat Apr 14, 2012 5:00 PM

Definitely a great post SeaGtGruff :thumbsup:

Thank you-- I just hope it's accurate! I made a booboo on the powers of 2, and I think I may have misunderstood how an IRQ interrupt is triggered-- after I posted I was reading that NMI is "edge-triggered" and IRQ is "level-triggered," but I didn't read up on what the difference is. Everything else is subject to correction, too, since I'm no computer engineer and I've cobbled together my knowledge of the 6502 and 6507 pinouts by searching the internet-- and we all know that everything posted on the internet is factual, accurate, unbiased, and complete!

Also, I'm not sure if this is what esplonky meant by "pinout," because I'm not sure how "pinout" relates to "memory information," unless it refers to the number of pins for the address bus. I'm hoping he'll clarify, and maybe post an example picture of what he's been looking at.

Here's a pinout I drew of the TIA chip (NTSC version):


I haven't gotten around to adding arrows yet. Many of the pin labels look the same or similar to labels on the 6502 pinout, but that doesn't necessarily mean they're the same ("SYNC" on the 6502 and "SYNC" on the TIA are totally different things). Also, the PAL version of the TIA has some differences. And there may be some variations between different releases of the NTSC version, because the TIA schematics contain notes about some lines being removed. There's also a slight confusion about the labels for two of the luminance pins, because the schematics label them one way but almost every other document flips them around.

Pins 1 and 22 are connected to ground (Vss). I'll get back to pin 22 in a moment, because it's one of the "chip select" pins.

Pins 20 and 23 are connected to power or voltage (Vcc). I'll get back to pin 23 in a moment, because it's another "chip select" pin.

Pin 11 is "OSC" for "oscillator" (sometimes labeled "XTAL" for "crystal"), and is connected to oscillator circuitry on the 2600's motherboard. This is an input line that feeds a 3579575 Hertz pulse to the TIA. (I'm not sure if that Hertz value is exact, or rounded, or truncated, so I'll be assuming that it's exact.) Thus, the OSC signal is basically a high-low pulse cycle that occurs about 3579575 times a second, which is the TIA's "pixel clock rate." The actual pixel clock signal is different than the OSC signal, but it's generated from the OSC signal-- I expect there is a tiny delay between them arising from the logic gates-- and I think they're inversions of each other. The TIA schematics show *two* clock signals for the graphics-- CLK and CLKP, with CLK being a slightly-delayed version of OSC, and CLKP being an inversion of CLK. The CLK signal is used for somethings (notably generating the clock 0 signal and the two horizontal clock signals), but the CLKP signal is used for other things.

Pins 4 and 26 are connected to the clock lines (the "phi" symbols). These are the same as for the 6502 and 6507, except they're reversed-- clock 0 is an *output* pin on the TIA, and clock 2 is an *input* pin.

The TIA takes the OSC signal and uses it to generate a clock 0 signal that has a rate one-third of the OSC rate-- about 1193191.7 Hertz. This is done with "divide by 3" circuitry, although the circuitry actually *multiples* the OSC signal by 3 in the sense that each high or low pulse is 3 times longer than they are in the OSC signal. It's called "divide by 3" because the Hertz rate of the clock 0 signal ends up being one-third of the OSC signal rate (1 clock 0 cycle is 3 times longer than 1 OSC cycle, which means there's one-third as many clock 0 cycles as OSC cycles per second). Whereas the OSC cycle is high-low, the clock 0 cycle is low-high, so they correspond to each other as follows:

101010101010 = OSC
000111000111 = clock 0

(The 0s and 1s are actually low and high voltage levels, not binary values as depicted here.) There's a slight delay between OSC and clock 0 due to gate delays as the clock 0 signal is being generated. The TIA hardware manual contains diagrams and a table showing the delays between the signals, but for this discussion I'll assume that the delays are 0, other than to mention that they do exist.

The TIA uses its clock 0 output pin to send the clock 0 signal to the 6507 via the 6507's clock 0 *input* pin. Then the 6507 uses the clock 0 signal to generate the clock 1 and clock 2 signals. The 6507 uses its clock 2 output pin to send the clock 2 signal to the TIA via the TIA's clock 2 *input* pin. The clock 0 and clock 2 signals are essentially identical-- both are low-high-- except for the slight delay between them, and the clock 2's low phase is slightly longer than its high phase.

The 6507 has no clock 1 output pin, and the TIA has no clock 1 input pin. Since the clock 1 and clock 2 signals are basically inversions of each other and are never both high at the same time, it's safe for the TIA and other chips or devices to assume that if clock 2 is low then clock 1 is high and vice versa.

Pins 27 through 32 are used for the TIA's 6-bit address bus. Since there are only 6 bits ("A0" through "A5"), the TIA can recognize only 64 addresses. Any other address bits that are output by the 6507 will be ignored by the TIA (well, almost), because those other address bits don't connect to any TIA pins-- except for two address bits that connect to two of the TIA's chip select lines.

Pins 21 through 24 are used for the TIA's "chip select" lines ("CS"). Pin 24 is "/CS0" or chip select 0, which is active-low. It's connected to the 6507's A12 pin (bit 12 of the 6507's address bus). But since it isn't connected to the TIA's address bus, it doesn't increase the TIA's addressable memory space. Instead, it's used to help the TIA know when the 6507 is talking to it.

Pin 21 is "/CS3" or chip select 3, which is also active-low. It's connected to the 6507's A7 pin (bit 7 of the 6507's address bus).

The other two chip select pins/lines are pin 23 ("CS1") and pin 22 ("/CS2"). CS1 is connected to power or voltage (Vcc), and is active-high (there's no bar over it). /CS2 is connected to ground (Vss), and is active-low. Since ground is always low, /CS2 is always active, but CS1 is active only when there's power going to it.

Chip select lines are used when multiple chips or devices are connected together so they'll be able to know when they're being talked to, so to speak. That is, the pins on the 6507 are connected to the pins on the TIA and 6532 (or RIOT chip). If the 6507 sends an address over its address pins and some data over its data pins, these signals go to the TIA and 6532 simultaneously, so the TIA and 6532 need to know, "Hey, Mr. 6507, are *you* talkin' ta *me*?" The chip select lines tell them this.

The memory address situation on the 2600 is rather complex. Although the 6507 CPU is the "master control," the program contained on the cartridge is really what controls everything, because it's a list of all the instructions that the CPU is supposed to execute. So let's say the 6507 reads the cartridge and its instruction is "STA %1110111101001010." That's binary for "STA $EF4A," which is hex for "STA 61258." So the cartridge is telling the 6507, "I want you to take whatever's in your accumulator and store it in memory location 61258." The 6507 gets the message and understands it perfectly, because the low byte and high byte for address 61258 came over the data bus, so all the bits in the address were received verbatim.

The 6507 then transmits whatever data is in its accumulator over its data bus, and tries to transmit address 61258 over its address bus-- except the 6507 has no output pins for A13, A14, and A15, so it *actually* transmits address 3914 (binary %0000111101001010, or hex $0F4A). This is the first source of the 2600's "memory mirrors." The cartridge (program) can tell the 6507 to read or write any memory location within the 6502's full 16-bit or 64K address space (addresses 0 through 65535), but the 6507 has no way to read or write any memory beyond the first 8K of memory locations because it can't transmit the values of A13, A14, and A15.

Let's think of this in terms of an office building for a moment. The TIA and the 6532 work in their own separate rooms, and both rooms have a screen, a message tube, and some indicator lights-- some chip select lights and a R/W light. The screen displays addresses from the 6507, like "3914," and the message tube is used to send or receive data. When the 6507 sends out an address and a data message, they go to both the TIA's room and the 6532's room.

One of the TIA's chip select lights is always on-- /CS2, which is connected to ground. Another chip select light is on only when the power is on-- we can think of it as indicating whether the office is open or closed (if the CS1 or power light is on, then working hours are in effect and the office is open for business). The other two chip select lights-- /CS0 and /CS3-- tell the TIA whether the address on the screen and the data in the message tube are meant for it or for some other employee in a different room. If both the /CS0 and /CS3 lights are on, then the TIA knows that *it* is supposed to do something-- but if /CS0 is off or /CS1 is off, then the TIA knows it's supposed to ignore anything on the screen and in the message tube. A fifth light-- a R/W light that can be one of two colors-- tells the TIA whether to take the contents of an address, put it in the message tube, and send it out ("read from 3914"), or take the contents of the message tube and put it in an address ("write to 3914").

Okay, so the 6507 has just displayed address 3914 on the TIA's and 6532's screens. The 6532 looks at its chip select lights and sees that one or more of them is off, which means it should ignore the 6507 for now. But the TIA looks at its chip select lights and sees that they're all on, so it knows it's supposed to do what the 6507 is telling it. It looks at the R/W light and sees that it's set to the "write" color, so it pulls the data out of the message tube. Then it looks at the screen to see which address it's supposed to store the data in.

However, the TIA's address bus has only 6 bits-- A0 through A5-- so it doesn't see address 3914 on its screen; instead it sees address 10 (binary %0000000000001010, or hex $000A). This is the second source of the 2600's memory mirrors-- the TIA and 6532 don't have 13 bits for their address lines like the 6507 does, so they can't use all 8K of the 6507's address space. I don't want to go too deep into memory mirrors right now, but hopefully the preceding discussion helps clarify that it's a two-part issue-- one part has to do with address bits that aren't connected to any pins of a chip's address bus, and the other part has to do with address bits that are connected to chip select pins rather than to address bus pins.

Pins 14 through 19, and pins 33 and 34, connect the TIA's 8-bit data bus to the 6507's data bus. Pins 14 through 19 are "D0" through "D5," respectively (labeled "D1" through "D6" on a few 2600 schematics). These are input-only pins, so they can receive data from the 6507 but they can't send data back from the TIA to the 6507. On the other hand, pins 33 and 34 ("D6" and "D7"-- labeled "D7" and "D8" on some 2600 schematics) are bidirectional pins, so they can receive data or send data.

Pin 25 is connected to the "R/W" line, so it tells the TIA whether the 6507 is executing a read instruction or a write instruction.

Pin 3 is connected to the "/RDY" line. Whereas the 6507's RDY line is an active-high input line, the TIA's /RDY line is an active-low output line. The cartridge (or program) actually controls when the TIA's /RDY line is supposed to be active (low, or 0), thereby telling the 6507 to pause and wait. When the 6507 fetches an instruction that tells it to write to the TIA's WSYNC register, the TIA gets the message and resets its /RDY line to 0, which tells the 6507 to pause. Then when the TIA's "horizontal sync counter" reaches the count that tells the TIA to begin its "horizontal blank period" the TIA sets its /RDY line back to 1, which tells the 6507 to resume executing program instructions.

Pins 35 through 40 ("I5" through "I0," respectively) are connected to the TIA's 6-bit input port. These are used for reading the four paddle controllers and the two joystick buttons.

Pins 12 and 13 ("AUD1" and "AUD0," sometimes labeled "AU1" and "AU0") are output pins for the TIA's two audio lines.

The rest of the pins are used for the video lines.

Pin 2 ("SYNC") outputs the composite sync signal for vertical sync and horizontal sync.

Pin 6 ("BLK") outputs the blanking signal for vertical blanking and horizontal blanking.

Pins 5, 7, and 8 are used to output the three bits for the luminance-- "LUM0" or "L0" (pin 8 ) is for bit 1 of the luminance, "LUM1" or "L1" (pin 5) is for bit 2 of the luminance, and "LUM2" or "L2" (pin 7) is for bit 3 of the luminance. (The TIA schematics show L0 as going to pin 5 and L1 as going to pin 8, but all other documents show them as being the other way around.) Although the 2600's color values appear to have 8 bits, with the lower nibble (or 4 bits) being used for the luminance, there is no connection for bit 0, which is why there are 8 luminances per hue rather than 16 luminances.

Pin 9 ("COL") is used to output the color signal-- including the colorburst signal. The NTSC 2600 can display 16 hues, but it doesn't output the hues as 4-bit values. Instead, it outputs a simple high-low signal that corresponds to the "color subcarrier cycle." The colorburst signal that's sent out during each horizontal blank tells the TV how to define the colorburst. In essence, there's a 360-degree "color wheel" that contains all of the displayable colors. We can think of colorburst as "angle 0," and all the other angles around the color wheel correspond to different colors-- thus, "angle 30" is a different color than "angle 78." The TIA applies a delay factor to each hue from 2 through 15 to create different colors. Hue 0 has no color, so the color delay has no relevance to it. Hue 1 is the same as colorburst (a slightly-greenish yellow on NTSC TVs), because there's no color delay applied to it. For hue 2 through hue 15, the amount of color delay that's applied to the color signal will determine what angle on the color wheel-- and therefore which color-- the color signal correspomds to. The following may help to make this clearer:

111111100000001111111000000011111110000000 = colorburst or hue 1 (no delay)
011111110000000111111100000001111111000000 = hue 2 (delay times 1)
001111111000000011111110000000111111100000 = hue 3 (delay times 2)
000111111100000001111111000000011111110000 = hue 4 (delay times 3)
000011111110000000111111100000001111111000 = hue 5 (delay times 4)
000001111111000000011111110000000111111100 = hue 6 (delay times 5)
000000111111100000001111111000000011111110 = hue 7 (delay times 6)
000000011111110000000111111100000001111111 = hue 8 (delay times 7)
100000001111111000000011111110000000111111 = hue 9 (delay times 8 )
110000000111111100000001111111000000011111 = hue 10 (delay times 9)
111000000011111110000000111111100000001111 = hue 11 (delay times 10)
111100000001111111000000011111110000000111 = hue 12 (delay times 11)
111110000000111111100000001111111000000011 = hue 13 (delay times 12)
111111000000011111110000000111111100000001 = hue 14 (delay times 13)
111111100000001111111000000011111110000000 = hue 15 (delay times 14)

And finally, pin 10 ("DEL") is an input pin that receives the color delay from a potentiometer on the 2600's motherboard. This potentiometer can be adjusted manually to increase or decrease the color delay. The 2600 field manual recommends that this potentiometer be set such that hue 15 is as close to hue 1 as possible.

Edit: Note that all information in this post comes with no warranty and no guarantee of accuracy. Corrections are welcome.

Edited by SeaGtGruff, Sat Apr 14, 2012 5:03 PM.

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