Definitely a great post SeaGtGruff
Thank you-- I just hope it's accurate! I made a booboo on the powers of 2, and I think I may have misunderstood how an IRQ interrupt is triggered-- after I posted I was reading that NMI is "edge-triggered" and IRQ is "level-triggered," but I didn't read up on what the difference is. Everything else is subject to correction, too, since I'm no computer engineer and I've cobbled together my knowledge of the 6502 and 6507 pinouts by searching the internet-- and we all know that everything posted on the internet is factual, accurate, unbiased, and complete!
Also, I'm not sure if this is what esplonky meant by "pinout," because I'm not sure how "pinout" relates to "memory information," unless it refers to the number of pins for the address bus. I'm hoping he'll clarify, and maybe post an example picture of what he's been looking at.
Here's a pinout I drew of the TIA chip (NTSC version):
I haven't gotten around to adding arrows yet. Many of the pin labels look the same or similar to labels on the 6502 pinout, but that doesn't necessarily mean they're the same ("SYNC" on the 6502 and "SYNC" on the TIA are totally different things). Also, the PAL version of the TIA has some differences. And there may be some variations between different releases of the NTSC version, because the TIA schematics contain notes about some lines being removed. There's also a slight confusion about the labels for two of the luminance pins, because the schematics label them one way but almost every other document flips them around.
Pins 1 and 22 are connected to ground (Vss). I'll get back to pin 22 in a moment, because it's one of the "chip select" pins.
Pins 20 and 23 are connected to power or voltage (Vcc). I'll get back to pin 23 in a moment, because it's another "chip select" pin.
Pin 11 is "OSC" for "oscillator" (sometimes labeled "XTAL" for "crystal"), and is connected to oscillator circuitry on the 2600's motherboard. This is an input line that feeds a 3579575 Hertz pulse to the TIA. (I'm not sure if that Hertz value is exact, or rounded, or truncated, so I'll be assuming that it's exact.) Thus, the OSC signal is basically a high-low pulse cycle that occurs about 3579575 times a second, which is the TIA's "pixel clock rate." The actual pixel clock signal is different than the OSC signal, but it's generated from the OSC signal-- I expect there is a tiny delay between them arising from the logic gates-- and I think they're inversions of each other. The TIA schematics show *two* clock signals for the graphics-- CLK and CLKP, with CLK being a slightly-delayed version of OSC, and CLKP being an inversion of CLK. The CLK signal is used for somethings (notably generating the clock 0 signal and the two horizontal clock signals), but the CLKP signal is used for other things.
Pins 4 and 26 are connected to the clock lines (the "phi" symbols). These are the same as for the 6502 and 6507, except they're reversed-- clock 0 is an *output* pin on the TIA, and clock 2 is an *input* pin.
The TIA takes the OSC signal and uses it to generate a clock 0 signal that has a rate one-third of the OSC rate-- about 1193191.7 Hertz. This is done with "divide by 3" circuitry, although the circuitry actually *multiples* the OSC signal by 3 in the sense that each high or low pulse is 3 times longer than they are in the OSC signal. It's called "divide by 3" because the Hertz rate of the clock 0 signal ends up being one-third of the OSC signal rate (1 clock 0 cycle is 3 times longer than 1 OSC cycle, which means there's one-third as many clock 0 cycles as OSC cycles per second). Whereas the OSC cycle is high-low, the clock 0 cycle is low-high, so they correspond to each other as follows:
101010101010 = OSC
000111000111 = clock 0
(The 0s and 1s are actually low and high voltage levels, not binary values as depicted here.) There's a slight delay between OSC and clock 0 due to gate delays as the clock 0 signal is being generated. The TIA hardware manual contains diagrams and a table showing the delays between the signals, but for this discussion I'll assume that the delays are 0, other than to mention that they do exist.
The TIA uses its clock 0 output pin to send the clock 0 signal to the 6507 via the 6507's clock 0 *input* pin. Then the 6507 uses the clock 0 signal to generate the clock 1 and clock 2 signals. The 6507 uses its clock 2 output pin to send the clock 2 signal to the TIA via the TIA's clock 2 *input* pin. The clock 0 and clock 2 signals are essentially identical-- both are low-high-- except for the slight delay between them, and the clock 2's low phase is slightly longer than its high phase.
The 6507 has no clock 1 output pin, and the TIA has no clock 1 input pin. Since the clock 1 and clock 2 signals are basically inversions of each other and are never both high at the same time, it's safe for the TIA and other chips or devices to assume that if clock 2 is low then clock 1 is high and vice versa.
Pins 27 through 32 are used for the TIA's 6-bit address bus. Since there are only 6 bits ("A0" through "A5"), the TIA can recognize only 64 addresses. Any other address bits that are output by the 6507 will be ignored by the TIA (well, almost), because those other address bits don't connect to any TIA pins-- except for two address bits that connect to two of the TIA's chip select lines.
Pins 21 through 24 are used for the TIA's "chip select" lines ("CS"). Pin 24 is "/CS0" or chip select 0, which is active-low. It's connected to the 6507's A12 pin (bit 12 of the 6507's address bus). But since it isn't connected to the TIA's address bus, it doesn't increase the TIA's addressable memory space. Instead, it's used to help the TIA know when the 6507 is talking to it.
Pin 21 is "/CS3" or chip select 3, which is also active-low. It's connected to the 6507's A7 pin (bit 7 of the 6507's address bus).
The other two chip select pins/lines are pin 23 ("CS1") and pin 22 ("/CS2"). CS1 is connected to power or voltage (Vcc), and is active-high (there's no bar over it). /CS2 is connected to ground (Vss), and is active-low. Since ground is always low, /CS2 is always active, but CS1 is active only when there's power going to it.
Chip select lines are used when multiple chips or devices are connected together so they'll be able to know when they're being talked to, so to speak. That is, the pins on the 6507 are connected to the pins on the TIA and 6532 (or RIOT chip). If the 6507 sends an address over its address pins and some data over its data pins, these signals go to the TIA and 6532 simultaneously, so the TIA and 6532 need to know, "Hey, Mr. 6507, are *you* talkin' ta *me*?" The chip select lines tell them this.
The memory address situation on the 2600 is rather complex. Although the 6507 CPU is the "master control," the program contained on the cartridge is really what controls everything, because it's a list of all the instructions that the CPU is supposed to execute. So let's say the 6507 reads the cartridge and its instruction is "STA %1110111101001010." That's binary for "STA $EF4A," which is hex for "STA 61258." So the cartridge is telling the 6507, "I want you to take whatever's in your accumulator and store it in memory location 61258." The 6507 gets the message and understands it perfectly, because the low byte and high byte for address 61258 came over the data bus, so all the bits in the address were received verbatim.
The 6507 then transmits whatever data is in its accumulator over its data bus, and tries to transmit address 61258 over its address bus-- except the 6507 has no output pins for A13, A14, and A15, so it *actually* transmits address 3914 (binary %0000111101001010, or hex $0F4A). This is the first source of the 2600's "memory mirrors." The cartridge (program) can tell the 6507 to read or write any memory location within the 6502's full 16-bit or 64K address space (addresses 0 through 65535), but the 6507 has no way to read or write any memory beyond the first 8K of memory locations because it can't transmit the values of A13, A14, and A15.
Let's think of this in terms of an office building for a moment. The TIA and the 6532 work in their own separate rooms, and both rooms have a screen, a message tube, and some indicator lights-- some chip select lights and a R/W light. The screen displays addresses from the 6507, like "3914," and the message tube is used to send or receive data. When the 6507 sends out an address and a data message, they go to both the TIA's room and the 6532's room.
One of the TIA's chip select lights is always on-- /CS2, which is connected to ground. Another chip select light is on only when the power is on-- we can think of it as indicating whether the office is open or closed (if the CS1 or power light is on, then working hours are in effect and the office is open for business). The other two chip select lights-- /CS0 and /CS3-- tell the TIA whether the address on the screen and the data in the message tube are meant for it or for some other employee in a different room. If both the /CS0 and /CS3 lights are on, then the TIA knows that *it* is supposed to do something-- but if /CS0 is off or /CS1 is off, then the TIA knows it's supposed to ignore anything on the screen and in the message tube. A fifth light-- a R/W light that can be one of two colors-- tells the TIA whether to take the contents of an address, put it in the message tube, and send it out ("read from 3914"), or take the contents of the message tube and put it in an address ("write to 3914").
Okay, so the 6507 has just displayed address 3914 on the TIA's and 6532's screens. The 6532 looks at its chip select lights and sees that one or more of them is off, which means it should ignore the 6507 for now. But the TIA looks at its chip select lights and sees that they're all on, so it knows it's supposed to do what the 6507 is telling it. It looks at the R/W light and sees that it's set to the "write" color, so it pulls the data out of the message tube. Then it looks at the screen to see which address it's supposed to store the data in.
However, the TIA's address bus has only 6 bits-- A0 through A5-- so it doesn't see address 3914 on its screen; instead it sees address 10 (binary %0000000000001010, or hex $000A). This is the second source of the 2600's memory mirrors-- the TIA and 6532 don't have 13 bits for their address lines like the 6507 does, so they can't use all 8K of the 6507's address space. I don't want to go too deep into memory mirrors right now, but hopefully the preceding discussion helps clarify that it's a two-part issue-- one part has to do with address bits that aren't connected to any pins of a chip's address bus, and the other part has to do with address bits that are connected to chip select pins rather than to address bus pins.
Pins 14 through 19, and pins 33 and 34, connect the TIA's 8-bit data bus to the 6507's data bus. Pins 14 through 19 are "D0" through "D5," respectively (labeled "D1" through "D6" on a few 2600 schematics). These are input-only pins, so they can receive data from the 6507 but they can't send data back from the TIA to the 6507. On the other hand, pins 33 and 34 ("D6" and "D7"-- labeled "D7" and "D8" on some 2600 schematics) are bidirectional pins, so they can receive data or send data.
Pin 25 is connected to the "R/W" line, so it tells the TIA whether the 6507 is executing a read instruction or a write instruction.
Pin 3 is connected to the "/RDY" line. Whereas the 6507's RDY line is an active-high input line, the TIA's /RDY line is an active-low output line. The cartridge (or program) actually controls when the TIA's /RDY line is supposed to be active (low, or 0), thereby telling the 6507 to pause and wait. When the 6507 fetches an instruction that tells it to write to the TIA's WSYNC register, the TIA gets the message and resets its /RDY line to 0, which tells the 6507 to pause. Then when the TIA's "horizontal sync counter" reaches the count that tells the TIA to begin its "horizontal blank period" the TIA sets its /RDY line back to 1, which tells the 6507 to resume executing program instructions.
Pins 35 through 40 ("I5" through "I0," respectively) are connected to the TIA's 6-bit input port. These are used for reading the four paddle controllers and the two joystick buttons.
Pins 12 and 13 ("AUD1" and "AUD0," sometimes labeled "AU1" and "AU0") are output pins for the TIA's two audio lines.
The rest of the pins are used for the video lines.
Pin 2 ("SYNC") outputs the composite sync signal for vertical sync and horizontal sync.
Pin 6 ("BLK") outputs the blanking signal for vertical blanking and horizontal blanking.
Pins 5, 7, and 8 are used to output the three bits for the luminance-- "LUM0" or "L0" (pin 8 ) is for bit 1 of the luminance, "LUM1" or "L1" (pin 5) is for bit 2 of the luminance, and "LUM2" or "L2" (pin 7) is for bit 3 of the luminance. (The TIA schematics show L0 as going to pin 5 and L1 as going to pin 8, but all other documents show them as being the other way around.) Although the 2600's color values appear to have 8 bits, with the lower nibble (or 4 bits) being used for the luminance, there is no connection for bit 0, which is why there are 8 luminances per hue rather than 16 luminances.
Pin 9 ("COL") is used to output the color signal-- including the colorburst signal. The NTSC 2600 can display 16 hues, but it doesn't output the hues as 4-bit values. Instead, it outputs a simple high-low signal that corresponds to the "color subcarrier cycle." The colorburst signal that's sent out during each horizontal blank tells the TV how to define the colorburst. In essence, there's a 360-degree "color wheel" that contains all of the displayable colors. We can think of colorburst as "angle 0," and all the other angles around the color wheel correspond to different colors-- thus, "angle 30" is a different color than "angle 78." The TIA applies a delay factor to each hue from 2 through 15 to create different colors. Hue 0 has no color, so the color delay has no relevance to it. Hue 1 is the same as colorburst (a slightly-greenish yellow on NTSC TVs), because there's no color delay applied to it. For hue 2 through hue 15, the amount of color delay that's applied to the color signal will determine what angle on the color wheel-- and therefore which color-- the color signal correspomds to. The following may help to make this clearer:
111111100000001111111000000011111110000000 = colorburst or hue 1 (no delay)
011111110000000111111100000001111111000000 = hue 2 (delay times 1)
001111111000000011111110000000111111100000 = hue 3 (delay times 2)
000111111100000001111111000000011111110000 = hue 4 (delay times 3)
000011111110000000111111100000001111111000 = hue 5 (delay times 4)
000001111111000000011111110000000111111100 = hue 6 (delay times 5)
000000111111100000001111111000000011111110 = hue 7 (delay times 6)
000000011111110000000111111100000001111111 = hue 8 (delay times 7)
100000001111111000000011111110000000111111 = hue 9 (delay times 8 )
110000000111111100000001111111000000011111 = hue 10 (delay times 9)
111000000011111110000000111111100000001111 = hue 11 (delay times 10)
111100000001111111000000011111110000000111 = hue 12 (delay times 11)
111110000000111111100000001111111000000011 = hue 13 (delay times 12)
111111000000011111110000000111111100000001 = hue 14 (delay times 13)
111111100000001111111000000011111110000000 = hue 15 (delay times 14)
And finally, pin 10 ("DEL") is an input pin that receives the color delay from a potentiometer on the 2600's motherboard. This potentiometer can be adjusted manually to increase or decrease the color delay. The 2600 field manual recommends that this potentiometer be set such that hue 15 is as close to hue 1 as possible.
Edit: Note that all information in this post comes with no warranty and no guarantee of accuracy. Corrections are welcome.
Edited by SeaGtGruff, Sat Apr 14, 2012 5:03 PM.