How to get started in GAL programming

[Wickeycolumbus]

Wasn't really sure where the best place to put this post is, but here we go. I know some people on here have experience programming PLDs, so if anyone could help me out that would be great.

 

I'm currently working on a project that requires some simple glue logic for selecting one of three 4 bit data sources as an input to a 74161 counter IC. I figured the least messy way to do this would be to implement my design on a GAL chip (probably a 20V8). I have a Genius G840 universal programmer coming in the mail soon that is said to program these chips, but I have no idea how to write the code to put on the chip. The design consists of about 14 AND gates and 8 OR gates which manipulate 15 inputs and create 5 outputs. Will this fit on a 20V8 in the first place?

 

If anyone could point me to some useful software, tutorials, or has any advice, that would be great.

 

Thanks in advance.

[+batari]

This might be best placed in the "hardware" forum.

 

Anyway, to get started, you will need to download some sort of HDL synthesizer. HDL means Hardware Description Language, and describes the logic that will go on the PLD (programmable logic device). The synthesizer part converts the HDL to a fusemap (such as a JEDEC file) that can be used to program the PLD.

 

I don't call then GALs, personally - to me that suggests Lattice Semiconductor's brand of SPLD. And, the 20v8 is basically obsolete - I don't know any still in active production. Better to stick to a 22v10 (and it's worth mentioning that a 22v10 is a superset of a 20v8, pin-compatible, and can be used in place of one with a proper fusemap.)

 

Anyway, common HDLs are VHDL and Verilog. If you're getting into hardware design, it's good to learn one of these languages eventually. These powerful HDLs allow for different levels of logic modeling (such as behavioral and structural).

 

Generally, behavioral coding is high-level coding that is abstracted from the hardware. It describes what the hardware does instead of specifying logic gates and connections. Although it can be used for SPLD programming, it sometimes doesn't synthesize as you expect it should.

 

Structural coding has you specify the gates, signals, and actual connections and such. It is a much lower-level sort of coding and it can be harder to do, but it gives you more control over the hardware.

 

I have used VHDL successfully for SPLDs, but VHDL and Verilog may be far more than you need. There are other HDLs like ABEL and CUPL that are better for smaller projects, but I personally have found an ancient DOS utility called Opal Jr that was very useful for SPLDs.

 

It includes a program called EQN2JED.EXE that converts basic logic equations to a JED file. It should run fine in DOSBOX if Windows or other operating systems don't like it. Quite helpfully, there is also a JEDEC decompiler called JED2EQN.EXE that will let you take an existing JED file and convert to an EQN file (which will show its logic equations.) This is very useful not just for learning but also to show you the proper format of the EQN file so you can create your own.

 

Before I can answer your question about your logic equations and whether they will fit on a SPLD, I need to know more about them. A 20v8 means that it can have up to 20 I/O lines, and up to 8 of them can be outputs, but this depends on what mode the SPLD is in. A typical SPLD can run in one of three modes - combinatorial, registered, or complex mode. I typically use registered mode for bankswitching as it gives you the clock input and can latch values but you lose an input.

 

In combinatorial mode, you get an extra I/O line in place of the clock so 15 inputs and 5 outputs may fit. But this depends on another limitation - the SPLD only has one level of logic inside - so if there are any internal signals that would require more than one level of product terms, you need to run each level of logic to an output, then feed the output back (can be done internally) to use in another logic equation. Obviously, this uses up one of your outputs.

 

But this is where a 22v10 may help - you get 22 I/O lines, of which 10 can be outputs. That extra allowance can make the difference, and really you should be using these devices in new projects anyway.

[+bob1200xl]

I use CUPL on Atmel chips. Atmel still supports CUPL - you can download it for free on the Atmel site. (along with tutorials)

 

Their CUPL is configured for just their chips, but they have a reasonably good selection of ICs that you can use it on. The same CUPL source can be used on 20 pin GALS and 84 pin CPLDs, so it's pretty flexible...

 

Bob

[Wickeycolumbus]

Thanks for all the advice Batari and Bob. Lots of great information. I did end up using a 22V10 since that's what they had at my local electronics store. I wrote the code in CUPL, though I really should look into stuff like VHDL. I'll probably be taking a class on it in the next couple years, but it's always good to get a head start.

 

The chip is for a simple 4 bit CPU I have been working on sporadically the last few years. It now executes 4 of the 16 planned instructions I'm currently having an issue with loading the program counter with a new address, rather than just incrementing/resetting it. I swear I'll finish it some day!

[+bob1200xl]

Atmel CPLDs have latches on each node that allow you to have both combinatorial and registered logic at the same time. This doubles the number of possible equations - sort of... The V750 is a nice 24-pin example of this feature. (with a 22V10 footprint) You can get these chips from Digi-key, Mouser and many other distributors on the Web. Usually no minimum, fast delivery.

 

Bob

[Bruce Tomlin]

A few years ago I was not happy that the only "freeware" that I could find back then were some old closed-source DOS programs.

 

So I made my own simple HDL for GAL chips. It's what I used when I did the bank switch chip for my 7800 cart board. It's a plain command-line C program.

 

http://xi6.com/files/palwiz-1.1.zip

[ziggystar]

I am trying to get into gal programming. I have a Amiga accelerator card with a bad pal. I downloaded wincupl and compiled the code. I uploaded to a gal20v8 but it doesn't work. Can anyone help? Does the code need to be changed to support gal? Or is wincupl not compatible with my gals? NSC brand.

 

http://www.thule.no/...0/pals/u504.pld

 

Thanks

[ziggystar]

http://www.thule.no/haynie/cpumods/a2620/pals/u504.pld

[dmercado55]

> I uploaded to a gal20v8 but it doesn't work.

 

​I looked at you PLD design specification and see if few things to look at.

 

If you are using the Atmel version of Wincupl, maybe you should use an ATF16V8 part.

 

Also add "DEVICE g16v8a;" after LOCATION in design specification otherwise you will run a 'device independent compile' and anything can happen.

 

Lastly if it still does not work, as your equations are only combinational logic, use the "Simple GAL Model" in the specification: DEVICE g16v8as;

 

If you want to use your National GALs you might want to use their software call Opal Jr. Scroll to bottom of this link: http://matthieu.benoit.free.fr/pld.htmto download. It may be a DOS program.

 

Or buy a copy here:

 

http://www.eetools.com/index.cfm?fuseaction=product.display&product_ID=323&ParentCat=22

 

-Dave

[dmercado55]

Whoops, I meant GAL20V8, Use DEVICE g20v8as.

[jdgabbard]

It doesn't matter which software package you use, Opal or Atmel. It will product a fictional equivalent JEDEC file. I've programmed several different makes with the JEDECs created by WinCUPL. Honestly, WinCUPL is better in my opinion due to the simulator.