chris_rainbow Posted August 6, 2012 Share Posted August 6, 2012 Hi all, Say STA WSYNC (4 cycles to execute) executes at cycle 100 the instruction finishes by 104; then I believe ANTIC takes 1 cycle to respond and halts the CPU at cycle 105. But ANTIC readies the CPU at cycle 105. So I would expect the CPU to be ready now. Is this the case? Otherwise I guess it could be the case that ANTIC first readies the CPU at 105 but then the STA WSYNC halts it immediately afterwards on the same cycle... I also believe DLIs fire at cycle 6. A NMI is raised at cycle 6 and and I think the current opcode finishes executing. Then another opcode should execute, and only then the NMI is serviced. True? Also I believe VCOUNT is updated at cycle 109 Any corrections/comments to the above will be welcome. Thanks, Chris. Quote Link to comment Share on other sites More sharing options...
Rybags Posted August 6, 2012 Share Posted August 6, 2012 (edited) Phaeron's Hardware Manual that can be downloaded from his Altirra page should have the relevant info. IIRC 6502 takes minimum 1 cycle to respond when RDY comes low, if it's doing a write operation it takes longer. The "impression" is that you get control back 1 cycle earlier than actually happens thanks to the delay. Antic DMA cycles throws further confusion into the mix, they will override what the CPU otherwise wanted to do. NMI - there's a whole kettle of fish there, the big issue is that Antic only holds it for a couple of cycles but an IRQ can inadvertantly mask it and cause it to be missed. Here's the text from Altirra HW Ref: DLI execution proceeds as follows: • ANTIC pulls NMI at cycle 8 at the beginning of a scan line, right after display list and P/M DMA. • The 6502 requires two cycles to acknowledge the NMI. • 0-6 cycles pass as the 6502 finishes the currently executing instruction. • Interrupt entry takes 7 cycles. Edited August 6, 2012 by Rybags Quote Link to comment Share on other sites More sharing options...
Bryan Posted August 6, 2012 Share Posted August 6, 2012 It's amazing how long the NMI bug went undocumented. I've seen several loading screens with DLI's that occasionally flickered and I guess no one ever nailed down the cause. The real fault was that the official 6502 documentation says that NMI should be held for at least two cycles, and that's what Atari did. If they'd held it longer it wouldn't have been a problem. I imagine that most other systems required an explicit reset of NMI rather than using a timed pulse. Quote Link to comment Share on other sites More sharing options...
Rybags Posted August 6, 2012 Share Posted August 6, 2012 Yep - not many applications would have NMI triggered at ~ 1/16,000th second. C64 uses NMI for Restore key and CIA Timers, Timers can be practically any period but they hold NMI until the program resets the status. Given that Antic is the only source for NMI and the timing is totally deterministic (even Reset key on 400/800 triggers at a specific point on the scanline) it's not like they'd have generated any conflict by using a longer period. Quote Link to comment Share on other sites More sharing options...
phaeron Posted August 6, 2012 Share Posted August 6, 2012 Say STA WSYNC (4 cycles to execute) executes at cycle 100 the instruction finishes by 104; then I believe ANTIC takes 1 cycle to respond and halts the CPU at cycle 105. But ANTIC readies the CPU at cycle 105. So I would expect the CPU to be ready now. Is this the case? Yes, in this case the 6502 is not held off at all. One cycle later, and it would be held off for an entire scanline. I also believe DLIs fire at cycle 6. A NMI is raised at cycle 6 and and I think the current opcode finishes executing. Then another opcode should execute, and only then the NMI is serviced. True? With missile DMA at 0 and WSYNC release at 105, the 6502 starts the interrupt sequence at the first instruction boundary opportunity starting at cycle 10. The one exception is if the NMI is enabled by a write to NMIEN exactly on cycle 7, in which case it's delayed to cycle 11. Also I believe VCOUNT is updated at cycle 109 Relative to missile DMA at 0, the incremented VCOUNT should be visible starting on cycle 110. Quote Link to comment Share on other sites More sharing options...
chris_rainbow Posted August 8, 2012 Author Share Posted August 8, 2012 I also believe DLIs fire at cycle 6. A NMI is raised at cycle 6 and and I think the current opcode finishes executing. Then another opcode should execute, and only then the NMI is serviced. True? With missile DMA at 0 and WSYNC release at 105, the 6502 starts the interrupt sequence at the first instruction boundary opportunity starting at cycle 10. The one exception is if the NMI is enabled by a write to NMIEN exactly on cycle 7, in which case it's delayed to cycle 11. To clarify with an example: cycle# 004 STA $1234 (+4 cycles) 006 NMI (DLI) raised 007 current opcode finishes 008 6502 services NMI, loads PC, etc (+7 cycles I believe...) 015 BIT $d40f (first opcode of interrupt routine executes) This look right? Thanks. Quote Link to comment Share on other sites More sharing options...
Rybags Posted August 8, 2012 Share Posted August 8, 2012 Sounds about right as a potential scenario, you can throw all kinds of DMA possibilities in too though. Quote Link to comment Share on other sites More sharing options...
chris_rainbow Posted August 9, 2012 Author Share Posted August 9, 2012 Slight change of topic: In the Hardware Manual it says "Memory refresh takes 9 cycles per scanline unless pre-empted by a hi-res graphics mode" Translation anyone? Quote Link to comment Share on other sites More sharing options...
phaeron Posted August 9, 2012 Share Posted August 9, 2012 The refresh cycles are positioned at fixed locations in the scanline, four cycles apart. However, if ANTIC needs to fetch playfield data on one of those cycles, it delays the refresh until the next available cycle. In modes 2-5, when ANTIC is pulling both character name and graphic data on the first scanline of a mode line, the DMA is thick enough that another refresh cycle time passes before a slot opens up, causing refresh cycles to be dropped. There is always at least one refresh cycle per scanline as refresh can be pushed all the way to the beginning of horizontal blank after playfield DMA is blocked. Quote Link to comment Share on other sites More sharing options...
chris_rainbow Posted August 10, 2012 Author Share Posted August 10, 2012 Thanks, it was the "hi-res graphics mode" bit that made me think it was alluding to something else. Quote Link to comment Share on other sites More sharing options...
Rybags Posted August 10, 2012 Share Posted August 10, 2012 That's what the docs say - it should in fact read "Hi-res text mode". ie - first line of Antic modes 2, 3, 4, 5. Number of Refresh cycles on "badlines" depends on DMA Width setting. It'd be a good idea to grab phaeron's hardware manual - he's got representations of many scenarios. http://virtualdub.org/downloads/Altirra%20Hardware%20Reference%20Manual.pdf Quote Link to comment Share on other sites More sharing options...
chris_rainbow Posted August 14, 2012 Author Share Posted August 14, 2012 It seems some registers can be changed mid scanline e.g. CHBASE; once character DMA has started it's unlikely to reload it. I imagine others like PMBASE are similar. Maybe HPOSx etc... and so on. Quote Link to comment Share on other sites More sharing options...
phaeron Posted August 14, 2012 Share Posted August 14, 2012 PMBASE yes, because it is only used for the 5 P/M DMA cycles at the beginning of the scanline. CHBASE, definitely not, because it is used for fetching every byte of character graphic data in text modes and there is no extra latch to hold the previous value. Changes to the P/M graphics registers in GTIA (HPOSPx/HPOSMx, SIZEPx/SIZEM, GRAFPx/GRAFM) also take place immediately. Quote Link to comment Share on other sites More sharing options...
Rybags Posted August 15, 2012 Share Posted August 15, 2012 Chbase changes will still work in the 20 column text modes, of course the DMA might upset whatever effect you're trying to generate. HPos on PMs works on a comparitor type operation, once an object starts to display you can change it's graphics or position without affecting it. Colour of course means just the 1/2 cycle delay until it takes effect. Quote Link to comment Share on other sites More sharing options...
+JAC! Posted August 15, 2012 Share Posted August 15, 2012 The rotator/split screen at the end of Sillythings is based on changing CHBAS with cycle accurray. It took 18 years to find out how to do it without bad lines, so it actually works :-) 1 Quote Link to comment Share on other sites More sharing options...
chris_rainbow Posted August 17, 2012 Author Share Posted August 17, 2012 Nice demo. Any way to skip the first part and go straight to the rotator/split screen? Quote Link to comment Share on other sites More sharing options...
MaPa Posted August 17, 2012 Share Posted August 17, 2012 Try youtube. Quote Link to comment Share on other sites More sharing options...
Rybags Posted August 17, 2012 Share Posted August 17, 2012 Atari800Win+ comes in handy there - turbo mode is generally 25 times or more faster than realtime on modern hardware. Quote Link to comment Share on other sites More sharing options...
+JAC! Posted August 17, 2012 Share Posted August 17, 2012 (edited) Try youtube. 30 FPS - aaaaargh, why do you do this to an Atari Demo :-) Edited August 17, 2012 by JAC! Quote Link to comment Share on other sites More sharing options...
chris_rainbow Posted August 17, 2012 Author Share Posted August 17, 2012 I'd like to test silly things on my emulator, but don't want to wait each time for the rotating thingys Quote Link to comment Share on other sites More sharing options...
MaPa Posted August 17, 2012 Share Posted August 17, 2012 Try youtube. 30 FPS - aaaaargh, why do you do this to an Atari Demo :-) Me? w1k did it... ! Quote Link to comment Share on other sites More sharing options...
+JAC! Posted August 17, 2012 Share Posted August 17, 2012 I'd like to test silly things on my emulator, but don't want to wait each time for the rotating thingys You could use this and make sure the generated screen is identical to Altirra. It's the timing core of the rotator. Silly-Split-Test.xex A save-state should also work, of course. Quote Link to comment Share on other sites More sharing options...
Heaven/TQA Posted August 22, 2012 Share Posted August 22, 2012 the rotator still kicks ass holy shit Quote Link to comment Share on other sites More sharing options...
Heaven/TQA Posted August 22, 2012 Share Posted August 22, 2012 the rotator still kicks ass holy shit Quote Link to comment Share on other sites More sharing options...
Tezz Posted August 22, 2012 Share Posted August 22, 2012 Yea, it was great to see it executed so well last year. It'd be cool to see a (non gtia mode) roto zoomer on a future A8 demo. The 64 guys have been doing them for years now. Quote Link to comment Share on other sites More sharing options...
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