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7800 Software Guide updated


RevEng

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Its an understatement to say that I'm not fond of reading through monospaced text docs. So I went ahead and converted the 7800 Software Guide into a PDF with a navigable index and proportional font for non-diagram text. I also added relevant TIA and 6532 info from the Stella doc, and an extra bit on reading two button joysticks.

I found this version is a lot easier on the eyes and better for quick look-ups, so I figured I'd share. Feel free to report any errors here.

7800 Software Guide updated.pdf

Edited by RevEng
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"6532
This chip is used only for I/O in 7800 mode, whereas in 2600 mode it also supplies access to all RAM and
timers. Its functions are more limited because its speed is not fast enough for normal operation. Any
access to this chip (joystick and switch I/O) will cause the microprocessor to slow to 1.19 MHz. The
ports and switches connected through the 6532 are: joysticks (directional), pause, game select, game
reset, and difficulty switches. The 64532 can be used to generate output through the joystick ports as
well. For address information on 6532 ports and switches, refer to Appendix 2, Standard 7800 Equates."

 

I'll keep going through the document and I'll Bold text to show possible additions, or things that may need attention/correction.

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"TIA
The TIA is only partly accessible in 7800 mode. While it occupies addresses x'0000' - x'003F' in 2600
mode, only the section at x'0000' - x'001F' is available in 7800 mode. The only significant (useable)
registers of these are the sound related registers and the input ports (fire buttons, paddle controllers).
Any access to the TIA will cause the processor to slow from 1.79 MHz to 1.19 Mhz."

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"GRAPHICS
MARIA does not employ the concepts of players, missiles, and playfield, as do the 2600 and 5200.
Instead MARIA uses an approach to graphics commonly used in coin-operated games. Each raster of
the display may be thought of as a bit map. This map is contained in an area of the MARIA chip called
the Line RAM. Information is first stored into the Line RAM, then later read from Line RAM and
displayed on the screen.
Consider for a moment just one raster of display. One would compose this raster's graphics by storing
data into Line RAM. This is done by specifying what data should be put at what horizontal location.
Graphics may be specified in small pieces, and overlapped. The order in which pieces of a raster are
specified determines object priority with the last object specified on top.
When graphics data is specified to be stored into Line RAM, it will reference any one of eight (8 ) color
palettes. Each pixel of data will take on any one of three (3) colors from the specified palette, or may be
turned off (transparent). Again, the Line RAM contains only one raster of graphics information. There
are actually two Line RAM buffers. While one is being read (displayed), the other is being written for
display in the next raster. This means that the construction of graphics for a raster may take as long as, but
no longer than, one raster, and that graphics must be stored into Line RAM on a raster by raster basis.
The only limit to the number, and size of objects on one scan line is the mount of time it takes to load
each into Line RAM, as all loading must occur during one scan line."

Edited by PAC-MAN-RED
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"Display List List
MARIA locates the Display Lists by reading a Display List List (referred to as DLL from now on). This
list is a series of 3 byte entries. Each entry points to a Display List. Included in each entry is a value
called OFFSET, which indicates how many rasters should use the specified Display List. OFFSET is
decremented at the end of each raster until it becomes negative, which indicates that the next DLL
entry should now be read and used. Each time graphics data is to be fetched OFFSET is added to the
specified High address byte, to determine the accrual address where the data should be found. This
allows one display list to specify many rasters of graphics. Without OFFSET the only approach to
graphics is to have a Display List for each raster, and a DLL for each Display List. Not only would this
use a lot of RAM, but it would also take quite a bit of processing time to manipulate these Display Lists
when objects move. Because OFFSET is added to HIGH address byte, each raster of graphics for an
object must be separated by x'100' bytes, or one page.

The group of rasters specified by one DLL entry is called a "zone." Again, the number of rasters in a
zone equals OFFSET+1. Larger zones mean less RAM is needed for DLLs, Display Lists and
Character Maps (see DMA MODES below). But upon consideration of how to use zones, you will
realize that to achieve smooth vertical motion each stamp must be padded at top and bottom with zeros.
For example, if the top raster of an object is to appear on the last line of a 16 high zone, it must have 15
lines of zeros above it. If that object is 8 pixels (2 bytes) wide, and its top line of data is located at
x'CF04', then you will need two bytes of zeros at x'D004', x'D104', x'D304',..., and x'DE04' (remember
that OFFSET decrements). As this can add up to many pages of zeros, you can specify that MARIA
should interpret certain data as zeros, even if it isn't. This is called "Holey DMA" because DMA will
see "holes" in the data that aren't really there. This can be enabled and disabled on a zone by zone basis
via a DLL entry. Holey DMA has been aimed at 8 or 16 raster zones, but will have the same effect for
other zone sizes. MARIA can be told to interpret odd 4K blocks as zeros, for 16 high zones, or odd 2K
blocks as zeros for 8 high zones. This will only work for addresses above x '8000'. This means that
these blocks can hold meaningful code, or tables, or graphics data used in a zone where Holey DMA is
not on."

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"Display Modes
The normal display mode is 160 mode, where the screen is divided into 160 pixels horizontally.
Typically graphics are done in 160x2 mode, where there are two color bits specified for each pixel, and
these two color bits refer to one of the eight palettes. Alternately, one may specify graphics in 160x4
mode, where there are four color bits per pixel. In this mode, each byte of graphics data would specify
only two (2) pixels of graphics. If higher resolution is preferred, 320x1 mode is the common choice,
where the screen is divided into 320 pixels horizontally and each pixel has one color bit. A more
colorful 320x2 mode is also available with two color bits per pixel.

Selection of a particular mode is accomplished through two separate operations: specification of
WRITE MODE, and specification of READ MODE. WRITE MODE is specified via the WM
bit of an extended (5 byte) header, as described above. READ MODE is specified via the CTRL
register. Both of these specifications will remain in effect until respecified. WRITE MODE is not
initialized by MARIA on power-up, and must be initialized by the cartridge before any display occurs.
The reason for specifying WRITE MODE via an extended header, is to allow the programmer to
change form 160x2 to 160x4 (or from 320x2 to 320x1, or vice-versa) during the DMA for a particular
scan line. For more information about modes see CTRL under REGISTERS.

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"CHARBASE

The CHARBASE register serves to specify the high address for any graphics data fetch in Character
(Indirect) mode. As you recall, The Character Map (pointed to by the Header in the Display List)
specifies the low address bytes of graphics data. Each of these low address bytes is concatenated with
the sum of CHARBASE + OFFSET, to give the full 16 bit addresses of where the graphics data should
be found[.] The CHARBASE register is WRITE ONLY."

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"CTRL
The CTRL register is a WRITE ONLY register used to control many of the modes of MARIA. Through
this register one can control whether the background color extends off the edge of the TV
(horizontally), beyond the area where graphics may be positioned; or whether the background color
stops at the horizontal limits of graphics and this border area appears black. This border area is an area
which appears undependably on various television sets.

CTRL also specifies whether characters (in Character mode) are one or two bytes wide. That is, in
Character (Indirect) mode, whether one, or two bytes of graphics data should be fetched at the address
pointed to by the Character Map entry and CHARBASE. The advantage of two byte characters is that
the same number of pixels can be specified with half as many Character Map entries. The disadvantage is

that when changing one character, twice as much of the screen is affected.

This register also controls whether the color burst signal is generated or not. If color burst is turned off,
the graphics are, of course, displayed in black and white, but with a greater clarity than if the gray scale
colors (x'00' - x'0F') were used.

Another bit of CTRL enables "Kangaroo" mode which eliminates transparency, so that any pixel of
color "0" will be background color, rather than transparent. For the derivation of this name see the
ATARI coin-op game Kangaroo.

DMA may be turned on or off via the CTRL register. At power-up DMA is off, and must be turned on
by the cartridge. This should not be done until after DPPL and DPPH have been stored (so that DMA
doesn't try to read a DLL from an undefined location). DMA should be turned on DURING VBLANK,
and never during the screen (rasters 16-258). If DMA is off the screen will continue to display the
background color."

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Continued...

 

320A mode is a true 320x1 mode. Pixels that are "on" refer to color two (2) of the specified palette.
Pixels that are off are transparent (or background color if "Kangaroo" mode is on). In 320B mode, which
is a 320x2 display mode, only the most significant palette bit is read. This means that either palette zero
(0) of palette four (4) is used. If "Kangaroo" mode is off, transparency will work differently for modes.
Consider a pair of 320-size pixels which make up one 160-size pixel. If either pixel of the pair is off, it
will not be transparent, but will take on background color instead. If both pixels are off, they will be
transparent. With "Kangaroo" mode on, things work as one would expect them to work in this mode.
Another factor concerning 320 modes is that the horizontal positioning still happens like 160 mode.
This means that in 320 modes, objects can only be positioned in 2 pixel increments.

 

Will continue tomorrow, need sleep now. :)

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Aye Skipper! :pirate:

 

Continued from the same area as my last two posts:

 

"320C mode allows more colors than 320A, but cannot really be called 320x2. In this mode, some of the
graphics data goes to specifying palettes, which is somewhat non-standard. If a pixel is on, it is color
two (2), and if it is off, it is transparent[,] or background color (same as 320A and 320B). The palette is
determined by combining the most significant palette. The palette for the leftmost pixel is specified by
P2,D3, and D2 (where P means a palette bit, and D means graphics data bit), and the graphics are
specified by D7. The next pixel right uses the same palette, and uses D6 for data. The next pixel right
uses a palette specified by P2, D1, and D0, and uses D5 for data. The rightmost pixel uses the same
palette, but D4 for data. The mapping for 320C mode is as follows:"

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Overview of TIA

SOUND

In TIA there are two audio circuits for generating sound. They are identical but completely independent
and can be operated simultaneously to produce sound effects through the TV speaker. Each audio
circuit has three registers that control a noise-tone generator (what kind of sound), a frequency
selection (high or low pitch of the sound), and a volume control.

Tone
The noise-tone generator is controlled by writing to the 4 bit audio control registers (AUDC0,
AUDC1). The values written cause different kinds of sounds to be generated. Some are pure tones like
a flute, others have various "noise" content like a rocket[,] motor[,] or explosion. Even though the TIA
hardware manual lists the sounds created by each value, some experimentation will be necessary to find
"your sound".

Frequency
Frequency selection is controlled by writing to a 5 bit audio frequency register (AUDF0, AUDF1). The
value written is used to divide a 30KHz reference frequency creating a higher or lower pitch of whatever
type of sound is created by the noise-tone generator. By combining the pure tones available from the
noise-tone generator with frequency selection[,] a wide range of tones can be generated.

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Port A – Hand Controllers

Port A is under full software control to be configured as an input or an output port. It can then be used
to read or control various hand-held controllers with the data bits defined differently depending on the
type of controller used.

 

...

 

Joystick Controllers

Two joysticks can be read by configuring the entire port as input and reading the data at SWCHA
according to the following table:

Data Direction Player
----- -------- ------
D7 right P0
D6 left P0
D5 down P0
D4 up P0
D3 right P1
D2 left P1
D1 down P1
D0 up P1

(P0 = left player, P1 = right player)A "0" in a data bit indicates the joystick has been moved to close that switch. All "1's" in a player's
nibble indicates that the joystick is not moving.

 

...

 

Paddle (pot) Controllers

Only the paddle triggers are read from the 6532. The paddles themselves are read at INPT0 thru INPT3
of the TIA. The paddle triggers can be read at SWCHA according to the following table :

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APPENDIX 1: 7800 MEMORY MAP

The memory map of the 7800, graphically illustrated on the next page, is in many ways similar to that
of the 2600, with the addition not only of MARIA, but also of 4K of RAM. This RAM is shadowed
(responds to other addresses) in zero, first, second, and third pages, the first two of these being
significant. You will notice the absence of the 128 bytes of 6532 RAM that make up zero page RAM in
the 2600. This is because of a speed discrepancy with the 6532. It's RAM has moved to an area in page
four (4) and may not exist in future versions of the MARIA chip, so it should not be used.

 

...

 

Where: X means "Don't Care[",] and A means the bits may be 1 or 0, but are not ignored. Entries 5 and 6
indicate that pieces of RAM from x'1800' - x'27FF' appear in zero, and first pages. The last entry
indicates that the last 2K block (x'2000' - x'27FF') is repeated at x'2800', x'3000', and x'3800' making
this 6K area a series of 2K shadows.

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APPENDIX 2: STANDARD 7800 EQUATES

INPTCTRL EQU X '01' INPUT PORT CONTROL ("VBLANK" IN TIA) WO
AUDC0 EQU X '15' AUDIO CONTROL CHANNEL 0 WO
AUDC1 EQU X '16' AUDIO CONTROL CHANNEL 1 WO
AUDF0 EQU X '17' AUDIO FREQUENCY CHANNEL 0 WO
AUDF1 EQU X '18' AUDIO FREQUENCY CHANNEL 1 WO
AUDV0 EQU X '19' AUDIO VOLUME CHANNEL 0 WO
AUDV1 EQU X '1A' AUDIO VOLUME CHANNEL 1 WO
INPT0 EQU X '08' PADDLE CONTROL INPUT 0 WO
INPT1 EQU X '09' PADDLE CONTROL INPUT 1 WO
INPT2 EQU X '0A' PADDLE CONTROL INPUT 2 WO
INPT3 EQU X '0B' PADDLE CONTROL INPUT 3 WO
INPT4 EQU X '0C' PLAYER 0 FIRE BUTTON INPUT WO
INPT5 EQU X '0D' PLAYER 1 FIRE BUTTON INPUT WO
BACKGRND EQU X '20' BACKGROUND COLOR R/W
P0C1 EQU X '21' PALETTE 0 - COLOR 1 R/W
P0C2 EQU X '22' - COLOR 2 R/W
P0C3 EQU X '23' - COLOR 3 R/W
WSYNC EQU X '24' WAIT FOR SYNC STROBE
P1C1 EQU X '25' PALETTE 1 - COLOR 1 R/W
P1C2 EQU X '26' - COLOR 2 R/W
P1C3 EQU X '27' - COLOR 3 R/W
MSTAT EQU X '28' MARIA STATUS RO
P2C1 EQU X '29' PALETTE 2 - COLOR 1 R/W
P2C2 EQU X '2A' - COLOR 2 R/W
P2C3 EQU X '2B' - COLOR 3 R/W
DPPH EQU X '2C' DISPLAY LIST LIST POINT HIGH WO
P3C1 EQU X '2D' PALETTE 3 - COLOR 1 R/W
P3C2 EQU X '2E' - COLOR 2 R/W
P3C3 EQU X '2F' - COLOR 3 R/W
DPPL EQU X '30' DISPLAY LIST LIST POINT LOW WO
P4C1 EQU X '31' PALETTE 4 - COLOR 1 R/W
P4C2 EQU X '32' - COLOR 2 R/W
P4C3 EQU X '33' - COLOR 3 R/W
CHARBASE EQU X '34' CHARACTER BASE ADDRESS WO
P5C1 EQU X '35' PALETTE 5 - COLOR 1 R/W
P5C2 EQU X '36' - COLOR 2 R/W
P5C3 EQU X '37' - COLOR 3 R/W
OFFSET EQU X '38' FOR FUTURE EXPANSION -STORE ZERO HERE R/W
P6C1 EQU X '39' PALETTE 6 - COLOR 1 R/W
P6C2 EQU X '3A' - COLOR 2 R/W
P6C3 EQU X '3B' - COLOR 3 R/W
CTRL EQU X '3C' MARIA CONTROL REGISTER WO
P7C1 EQU X '3D' PALETTE 7 - COLOR 1 R/W
P7C2 EQU X '3E' - COLOR 2 R/W
P7C3 EQU X '3F' - COLOR 3 R/W

SWCHA EQU X'280' P0,P1 JOYSTICK DIRECTIONAL INPUT R/W
SWCHB EQU X'282' CONSOLE SWITCHES R/W
SWACNT EQU X'281' I/O CONTROL FOR SWCHA R/W
SWBCNT EQU X'283' I/O CONTROL FOR SWCHB R/W

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APPENDIX 3: DMA TIMING

There is some uncertainty as to the number of cycles DMA will require, because the internal MARIA
chip timing resolution is 7.16 MHz, while the 6502 runs at either 1.79 MHz or 1.19MHz. As a result, it
is not known how many extra cycles will be needed in DMA startup/shutdown to make the 6502 happy.
It is even possible for the 6502 to be in the middle of a long (TIA or 6532) access when it is to be
halted, so the uncertainty goes up to about 5 cycles.
All times listed below refer to 7.16 MHz cycles.

DMA startup 5-9 cycles
Header (4 byte) 8 cycles
Header (5 byte) 12 cycles
Graphics Reads:
Direct 3 cycles
Indirect/1 byte 6 cycles
Indirect/2 byte 9 cycles
Character Map access 3 cycles
Shutdown Times:
Last line of zone 10-13 cycles
Other lines of zone 4 - 7 cycles

End of VBLANK is made up of a DMA startup plus a Long shutdown.

DMA does not begin until 7 CPU (1.79 MHz) cycles into each scan line. The significance of this is that
there is enough time to change a color, or change CTRL before DMA begins, and during HBLANK
(before display begins). This figure should, however, be included in any DMA usage calculations.
Another timing characteristic is that there is one CPU (7.16 MHz) cycle between DMA shutdown and
generation of a DLI.

Edited by PAC-MAN-RED
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Its an understatement to say that I'm not fond of reading through monospaced text docs. So I went ahead and converted the 7800 Software Guide into a PDF with a navigable index and proportional font for non-diagram text. I also added relevant TIA and 6532 info from the Stella doc, and an extra bit on reading two button joysticks.

 

I found this version is a lot easier on the eyes and better for quick look-ups, so I figured I'd share. Feel free to report any errors here.

 

attachicon.gif7800 Software Guide updated.pdf

 

Nice work on cleaning up the guide! Can you add the information about the control register....

 

http://atariage.com/forums/blog/52/entry-5118-7800-control-register/

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