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TMS-9900 CP/M?


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#76 JamesD OFFLINE  

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Posted Tue Sep 5, 2017 9:38 AM

Suit yourself. I'm just saying that I don't know who came to that conclusion originally. I've just seen it repeated in many cases.

I've seen it repeated a lot... and I've never seen a reference to who originally said it.
That doesn't make it true.



#77 apersson850 OFFLINE  

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Posted Mon Sep 11, 2017 1:11 PM

Yes, looking in the TMS 9900 timing diagram, one can see at it uses two clock cycles to access memory, even when there's no wait state involved. It seems that they should be able to access an internal register faster than that.

Does anyone have any similar performance data for the TI 990/9 CPU?



#78 pnr OFFLINE  

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Posted Sat Sep 16, 2017 5:41 PM

Can anyone even cite who originally said this?

 

 

I think I can answer this: Daren Appelt, the engineer that designed the TI960, TI980 and TI990 mini computers.

 

First of all, think of the context of the time: most of the 16-bit mini's were designed in the late 60's using the then new TTL logic chips and core memory. 

 

The CPU's were split over 5-20 boards in a rack, and typically clocked at between 3 and 10 Mhz (the maximum speed that such a context would allow) leading to say a typlcal data path cycle time of 200-350 ns. The core memory had a typical cycle time of 800 to 1200 ns. Often the designs would use an analog delay line to measure out the access time of the core memory and stall the CPU as it waited for data from memory. The PDP-11, the Nova, the HP2100, the 316, etc. all shared these characteristics. Things like caches were too expensive to implement and did not appear on this class of computer until the mid/late 70's.

 

In the 1960's having registers in memory was not unusual in mini computers, due to the cost of building registers from individual flip-flops: adding 16 registers of 16 bits each would have taken an entire board full of 7475 TTL chips. For example, the PDP-8 (which pre-dates the TTL era) had its registers in memory. Often only a few H/W registers existed, augmented by a bank of easily addressed memory locations (e.g. on the Nova, and the 6502 "page 0" is an echo of this.).

 

Then came semiconductor memory in the early 70's (and Daren had some involvement in that within TI, holding a few patents etc.). This soon had the potential to build main memory with a cycle time of 250-500 ns, the same as the cycle time of the 5-20 board CPU's of the era. Now, suddenly, it became possible to have registers in memory and not pay a hefty price in performance. In this context, the maxim "memory is as fast as CPU registers" was true, and the 990 was proposed and designed in 1973.

 

The novelty in the TI990 design was the idea of a workspace pointer and placing the register bank anywhere in memory. This was mostly useful in the context of the main production computer languages of the era, Cobol and Fortran. In these languages there was no recursion and each subroutine could be allocated its own block of registers. This was on optimisation over what happened on e.g. an IBM360, where each subroutine started with an instruction to save the registers to a block of memory, and ended with an instruction to reload them from that memory block. The TI990 was successful as a Cobol office machine, with some 100,000 units sold (incl. the desktop System 200/300/etc.).

 

Daren was also the person who noticed that the TI990 CPU could fit on a single chip with the then current technology, and it came to be in 1975. This was also the undoing of the design: with the CPU shrunk from several boards in a rack to a single chip, adding CPU-based registers became almost zero cost and again had a speed advantage. The TI990 design hence had a very short window in computer history where it made sense.

 

In the 80's several designs were tried that had multiple register banks integrated in the CPU, notably in the RISC world (e.g. the Sun Sparc). As time progressed, it turned out that having a smallish block of registers at the traditional instruction set level, an optimising compiler and microcode with advanced pipeline techniques (register renaming etc.) is the best route to performance for our current software base and it squeezed out all other designs.



#79 JamesD OFFLINE  

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Posted Sun Sep 17, 2017 11:05 AM

Well, I'm pretty sure that the speed of flip flops increased at the same rate as SRAM since SRAM is made with flip flops.
DRAM uses a transistor and a capacitor, so... maybe faster... but I have my doubts due to the required refresh.
You would have a slightly faster access time only to be replaced with regular big waits.
So I think this is still a board size/cost rather than speed issue.



#80 mizapf OFFLINE  

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Posted Sun Sep 17, 2017 1:42 PM

SRAM is typically much faster than DRAM; in particular, you can find SRAM in cache memory. DRAM requires a periodic refresh; it is much simpler to build (1T1C cell = one transistor, one capacitor), but you have to actually charge/discharge the capacitor of the cell.



#81 JamesD OFFLINE  

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Posted Sun Sep 17, 2017 5:45 PM

SRAM is typically much faster than DRAM; in particular, you can find SRAM in cache memory. DRAM requires a periodic refresh; it is much simpler to build (1T1C cell = one transistor, one capacitor), but you have to actually charge/discharge the capacitor of the cell.

My thought as well, but I don't know what things were like in the late 60s.  

I think DRAM would still be slower but...I have nothing to base that on from that time period.



#82 Ksarul OFFLINE  

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Posted Sun Sep 17, 2017 9:10 PM

Note that Core Memory was still in heavy use until about 1975 or so. . .as the first widely successful DRAM chips didn't show up until 1973. The earliest Intel DRAM chips came in 1970, but they had a lot of issues at first. That said, a lot of design decisions made in the early to mid 1970s still reflected an environment with core. Hard core military and science applications still used a lot of it even into the mid 1980s (Challenger's computers used core memory until the accident that destroyed it in 1986). It was a time of technology transition, so a lot of what was going on then didn't have a long shelf life, engineering-wise.



#83 apersson850 OFFLINE  

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Posted Today, 2:02 AM

What pnr writes above makes sense all the way. And even if flip-flops got faster too, the speed limitation came from the CPU being spread across a number of circuit boards, so that didn't really help.

Then the TMS 9900 just put the same design on one chip, without taking into account that such an integration kind of invalidated the whole idea.

 

Take a look here for a patent application by TI in 1975. Mr. Appelt didn't file it, but he's referenced as he has applied for a patent for an asynchronus bus communication system, later known as TILINE.


Edited by apersson850, Today, 2:12 AM.


#84 JamesD OFFLINE  

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Posted Today, 12:25 PM

What pnr writes above makes sense all the way. And even if flip-flops got faster too, the speed limitation came from the CPU being spread across a number of circuit boards, so that didn't really help.

Then the TMS 9900 just put the same design on one chip, without taking into account that such an integration kind of invalidated the whole idea.

 

Take a look here for a patent application by TI in 1975. Mr. Appelt didn't file it, but he's referenced as he has applied for a patent for an asynchronus bus communication system, later known as TILINE.

Actually, I don't think it does.
1.  It does not account for the read-modify-write requirement than guarantees RAM has to be slower.
2. The 990/10 ran at 4.5MHz.  You shouldn't have buss speed issues from board to board until much higher speeds.
3. If there were speed issues across boards, that would also impact accessing RAM which would be... on other boards.






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