Atari 600XL SRAM

[Mercenary6502]

Hi,

 

I recently purchased an Atari 600XL with of course, the stock 16k RAM. I've already done some mods to it and I'm now limited to the little RAM. So obviously I want to upsize the ram, and 64k would be enough to satisfy me. I understand that it uses a dual chip dynamic 4-bit ram setup, unlike the 1-bit 8 chip setup in 800XL's. Unfortunately, all I have is plenty of 4164 chips, and no 4464's. Of course it's still possible to find 4464's, but they're becoming pretty scarce I would like to do something more modern. Hence, the title of this fourm.

 

I haven't studied on DRAM too much, but I know they need to be refreshed and that the address lines are multiplexed unlike the parallel SRAM I want to use. I don't have the schematics but I assume there's some refresh and multiplexing circuitry, and of course the address logic. Other than the enable pins, could adding SRAM be as simple as removing/bypassing the refresh and miltiplexing circuity and wiring the address pins dirrectly to the address logic? If that makes sense.... Like I said, I don't have the schematics so I don't know what the address logic looks like.

 

The other idea I've had is to build an SRAM module for the parallel port with the correct address logic and add-on to the existing DRAM. I've also considerd using the 4164 ram I have somehow.

 

 

What do you guys think?

 

(I'm not looking for any pre-made easy solutions. I want to use what I have even if it means plenty of manual wiring. I like the experience!)

 

Thanks!

Edited September 24, 2015 by programmer6502

[Mercenary6502]

I just found the schematics... I can understand things more clealy now.

Edited September 24, 2015 by programmer6502

[BillC]

There is the Atari 1064 which attaches to the PBI and gives the 600XL 64K RAM using 4164 chips, this is available from Best Electronics, and the schematic is available here.

 

ctirad already designed a 320K PBI static RAM upgrade similar to what you mention.

http://atariage.com/forums/topic/162420-ram-320xl/

[Mercenary6502]

Thanks for the links. 320k is a lot of ram!

[+bob1200xl]

If we could see your schematic, we could make useful comments. It is a pretty simple mod - there is no need to match addresses or data, just wire them in the easiest alignment - use the CI pin on the MMU anded with PH02 clock to select the SRAM - pull out all the DRAM and memory multiplexing ICs. If you are going to do a RAMBO controller, you'll need a little more hardware.

 

Bob

[Mercenary6502]

Really? That would be great!

 

The schematics I found are avilable in the first link BillC provided. In the 600XL zip

[+bob1200xl]

I was thinking of a schematic for a 512K upgrade...

 

Bob

[Mercenary6502]

Ah. That's a crazy amount of RAM for one of these computers! I'm planning on 64K for now though so I don't have to mess with bankswitching. So in your last post, why do you AND the CI pin of the MMU with the "PH02" clock to selelct the SRAM chip? How does that work? And what does "CI" stand for in the MMU? The reason I ask is clocks obviously pulse consistently high and low, rather than just a simple logic high or low. I'm just curious.

 

BTW, completely disregard what I said about address logic in my first post everyone. I reviewed a book I have and what I was thinking was completely off. I’m only confusing myself haha.

Edited September 25, 2015 by programmer6502

[Van]

This may be of use to you

http://atari.neostrada.pl/static/static.html

This page is in Polish but Google Translate does ok, you should be able to get the main points. Uses a 128KB SRAM but only uses 64K of it.

Yogi

[Mercenary6502]

I like the looks of that one, and was able to get enough from it. So I might just do that, thanks!

[Mercenary6502]

Upon further examination there's one thing I don't understand. On the diagram in the website, it looks to me like you're supposed to connect pin 10 of U18 (a 74LS08) to pin CS of the SRAM. The problem is, U18 in my 600XL is a SN74S32N, not a 74LS08. The only 74LS08 I can see is U7! It's weird though, even the 600XL schematics show U18 is a 74LS08.....

 

Any ideas? I could have misinterpreted.

[Roydea6]

The schematic on the web site is illustrating the 800xl and 65xe motherboards..

[+Larry]

http://www.horus.com/~hias/atari/#sram512k

 

Quite a few people have commented favorably about this one. I have a very similar commercialized version of this, and it works very well.

 

...Lots of wire, and not so many parts and pretty much "roll your own." Seems to fit your requirements, except maybe "too big?"

 

-Larry

[+bob1200xl]

CI is CAS Inhibit - basically a RAM Select line generated by the MMU. At the beginning of the clock cycle (when PH02 falls), there is a lot of garbage changing state on the data, address, and control lines. If you are interfacing a fast chip to the system bus, you need to make sure it does not 'see' all the 'junk'.

 

If all you want is 64K, you should just use the 64Kx4 DRAM. I can't recommend hand wiring all those nets.

 

You might want to consider using the BASIC chip site to mount an SRAM, but then you need to get into the MMU.

 

 

Bob

 

 

Ah. That's a crazy amount of RAM for one of these computers! I'm planning on 64K for now though so I don't have to mess with bankswitching. So in your last post, why do you AND the CI pin of the MMU with the "PH02" clock to selelct the SRAM chip? How does that work? And what does "CI" stand for in the MMU? The reason I ask is clocks obviously pulse consistently high and low, rather than just a simple logic high or low. I'm just curious.

 

BTW, completely disregard what I said about address logic in my first post everyone. I reviewed a book I have and what I was thinking was completely off. I’m only confusing myself haha.

[Van]

Upon further examination there's one thing I don't understand. On the diagram in the website, it looks to me like you're supposed to connect pin 10 of U18 (a 74LS08) to pin CS of the SRAM. The problem is, U18 in my 600XL is a SN74S32N, not a 74LS08. The only 74LS08 I can see is U7! It's weird though, even the 600XL schematics show U18 is a 74LS08.....

 

Any ideas? I could have misinterpreted.

Well, after reviewing the 600XL shema from BillC's link, /CI is generated at MMU U2.16, the PAL 16L8, shown on sheet 2. But for the life of me, I can't find this signal on any of the other sheet in the set.

The text of Toriman's site does mention " Available on leg 16 MMU signal / CI (CAS Inhibit)" . On his drawing he is picking off /CI from the AND gate input pin 10 (On the 800XL, EXT ENB is also applied to this pin). So you should be able to get it directly from the MMU chip U2.16.

Hope this helps,

Yogi

[Mercenary6502]

CI is CAS Inhibit - basically a RAM Select line generated by the MMU. At the beginning of the clock cycle (when PH02 falls), there is a lot of garbage changing state on the data, address, and control lines. If you are interfacing a fast chip to the system bus, you need to make sure it does not 'see' all the 'junk'.

 

If all you want is 64K, you should just use the 64Kx4 DRAM. I can't recommend hand wiring all those nets.

 

You might want to consider using the BASIC chip site to mount an SRAM, but then you need to get into the MMU.

 

 

Bob

 

 

Oh, I see. That makes sense.

[Mercenary6502]

Well, I agree with Bob about the wiring. I like things to be clean and reliable, but it has been done. Here's a project of mine that I did before (which already consumes the basic socket).

 

Original prototype:

 

 

Lasted REV 1 board:

 

 

This is a Basic rom adapter that I designed myself to replace the frustrating REV B with C (if any of you like to program with Basic). And while I was at it, I added three built in 8k games that can be selected with the two switches. As you can probably tell, I prototyped and tested it with a 800XL, but I currently have one installed in my 600XL as well and it works great. (Note: I did make a board design mistake by not providing ground holes for the switch wires. This will be fixed on my next run of boards.)

 

So about the RAM, I'll weigh out the options. I'll probably avoid the DRAM because I might be doing this more than once and need parts that are readily available.

 

I really appreciate everyone that as taken the time to help!

[Mercenary6502]

Well I gave it a try following the link Yogi provided. Didn't get any smoke or sparks, but I did get a yellow screen.... I checked my work four times and nothing. I eventually went back to the original DRAM configuration (by simply disconnecting a few wires and inserting the old chips back in) and it boots up just fine like before. Any ideas? Does the yellow screen give any clues?

 

Thanks

[Mercenary6502]

My bad! Used a NAND gate instead of an AND. Replaced that and I'm now getting a black screen. Yay!

 

(Edit: screen goes from yellow to black)

Edited September 27, 2015 by programmer6502

[Kyle22]

Well, I don't know enough about your particular situation to say much, but if the screen changes, it may mean that the 6502 is running the OS code long enough to init the GTIA. After that, who knows...

[Mercenary6502]

Yeah that's a possibiltiy. It seems like the RAM is filling with something, because it takes a few seconds to clear after powering off the system. If I power off and quickly power back on, I get the black screen. If I power off and wait like three seconds, I get the yellow then black screen like I was mentioning. I do have some doubts about the logic, but it could be something else. Well... I'll carefully play with it more and see if I can't get it to boot.

[Mercenary6502]

Well I made some progress! I can now get the computer to boot and run dependently on my SRAM chip! The only downside is it's only using 16k of it. The first change I made was tie OE of the SRAM to just ground instead of NANDing "Phi2" and "R/W" to it like the website shows that Van provided. The other thing I did was tie "CS" to the DRAM's "CAS" line on pin 8 of U18. Obviously, that's why it's only using 16k of my SRAM since it probably disables the chip past that point. As far as "WE" goes, the logic on that website seems to work just fine.

 

So now I know that the problem is CS. I just haven't been able to get it work using anything other than the old CAS line. I've tried using CI from pin 16 of U2 (the MMU) by both wiring it directly to the SRAM's CS pin, and by ANDing it with the PH02/Phi2 clock. No go! What do you guys think? I really need more RAM so I can play Donkey Kong!! (Which on disk BTW, since I don't have the cart)

 

Thanks

[Van]

Well I made some progress! I can now get the computer to boot and run dependently on my SRAM chip! The only downside is it's only using 16k of it. The first change I made was tie OE of the SRAM to just ground instead of NANDing "Phi2" and "R/W" to it like the website shows that Van provided. The other thing I did was tie "CS" to the DRAM's "CAS" line on pin 8 of U18. Obviously, that's why it's only using 16k of my SRAM since it probably disables the chip past that point. As far as "WE" goes, the logic on that website seems to work just fine.

 

So now I know that the problem is CS. I just haven't been able to get it work using anything other than the old CAS line. I've tried using CI from pin 16 of U2 (the MMU) by both wiring it directly to the SRAM's CS pin, and by ANDing it with the PH02/Phi2 clock. No go! What do you guys think? I really need more RAM so I can play Donkey Kong!! (Which on disk BTW, since I don't have the cart)

 

Thanks

Good to hear your are making progress on this. On Toriman's page, he is replacing the stock 64K of a 800XL, and with a 600 it's going to be a little more work to upgrade to 64K.There has to be some added logic to map the 64K of ram like the 800XL does. Without any added logic you'll see only the ram of the stock configuration.

Here is a 64K upgrade with 4464 DRAMs, to give some idea of what will have to be done but for the SRAM

http://www.atarimax.com/freenet/freenet_material/12.AtariLibrary/2.MiscellaneousTextFiles/showarticle.php?108

Seems to me this mod is expanding the address range of the CAS from 16K to 64K, which is what you need but have no idea if it would be as simple as doing the mod without the DRAMs.

Yogi

EDIT link address

Edited October 2, 2015 by Van

[Van]

OK so I compared the 64K DRAM mod to the Schema;

1. It's appling A14 and A15 to the '158s. You wouldn't need to do this 'cause no DRAMS

2. The OR gate Pin 9 is hardwired to GND. This gate controls when CAS is passed to the DRAMs, by default this is only when A14 and A15 are low.

 

So it seems to me, if the SRAM is working with the default CAS driving /CS, by doing the change to U18.9 you should see the same amount of RAM as the 64K DRAM mod would. I think the MMU will lower the total amount when mapping in I/O and ROMs. Maybe?

Yogi

Edited October 2, 2015 by Van

[Wrathchild]

One tip for 4464 chips is to look for old ISA graphics cards as these were often used on them