By the way, the schematics can be found on the SNUG page: http://home.arcor.de...bwg/php1245.pdf
Maybe someone would like to have a look? Here is a description that you may be able to follow on the schematics.
On the left-hand side, near the bottom, there is the data bus (D0-D7), above there is RDBENA* and READY. When READY=0, the CPU enters wait state. The tri-state buffer (U8C) delivers 0 when its control pin (pin 10) is 0. For that to happen, all inputs of U7B (OR gate up-right) must be 0. Pin 4 of U7B goes to the PAL and is 0 when the controller chip is accessed. Pin 5 is the endpoint of the signal WAITen* connected to Q2 of the U13 latch (go left from the output gate DS1* on the right side). When this bit is set, it is inverted and arrives as a 0 at the OR gate. This bit is set by a SBO 2.
So far, the READY line will only be lowered when a memory access to the controller is done (5FFx) and we have a preceding SBO 2. It only depends on the third input of the OR gate (pin 3). This one is connected to the output of a NAND (U23B) that gets its inputs from A13, A14, A15, and from another OR gate (U7A) whose output is inverted by a gate in between. The NAND will only deliver 0 when all of its inputs are 1. This implies that A13, A14, A15, and that OR gate are all delivering ones. The OR gate's inputs are the controller lines IRQ, DRQ, and the output of the motor monoflop, inverted.
So I would understand the operation as follows:
- The controller is reading a sequence of bits from the disk and stores them in a shift register that will be readable via the data register port (5FF6).
- As long as DRQ is 0 and the motor is turning, the data register is not ready to be read. This lock is enabled by a previous SBO 2. In order to react in time, the data register read operation must be initiated, and the processor must be locked until the byte is available. The exactly same thing is done in the TI disk controller.
- Until ready, U7A delivers 0, U23A inverts to 1. In order to arrive as a 0 at the U7B OR gate, A13, A14, A15 must all be 1. This is only possible when reading 5FF7. That is, the processor is locked while reading 5FF7.
- When the data register is full (8 bits read), DRQ is set to 1. This will arrive at U23B as a 0, the output will become 1, which eventually inhibits the tri-state buffer, and READY is released. Consequently, the datamux completes the first read operation, and the starts the second one at 5FF6.
- Now since A15 is 0, U23B will always deliver 1, regardless of the state of DRQ. The processor will not be locked during the 5FF6 access.
See my problem? Since the Geneve never accesses the 5FF7 address, the processor will never be locked while waiting for the incoming bits. The TI disk controller, in contrast, simply ignores the odd accesses and enters wait states on the 5FF6 address.
I seem to remember Michael Becker once ranting about the Geneve "doing it the wrong way, how should we know".