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Interrupt Service Routine and the RS232

RS232 interrupts ISR TIMXT

35 replies to this topic

#26 marc.hull OFFLINE  

marc.hull

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Posted Thu Apr 20, 2017 8:08 PM

This is of course one reason for that I, when I made my 32 K RAM internal 16-bit memory expansion also allowed it to overlap all other memory in the machine. Thus I can copy console ROM to RAM, switch to RAM and change the vectors as I like.


Questions...
When you did this how did you make the memory map dynamic ? Rom was hard wired as well as $4000 and $6000 so I would think that there was major butchery on the mobo but perhaps there was some trick that worked?

How did you keep the ports intact?

#27 apersson850 OFFLINE  

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Posted Fri Apr 21, 2017 4:06 AM

Now I don't have the schematics in front of me, but the principle is to fiddle with the chip select lines. Since all memory is connected to the same data bus, the chips that actually are active are selected. The other chips go to tri-state output level.

What I did was to add to the chip select decoding, to involve also a CRU bit for each bank. At power up, chip select goes to ROM, expansion cards, cartridge memory, ports and the new internal 16-bit wide memory expansion.

But setting the appropriate CRU bit, I can modify chip select to go to new RAM instead of ROM, cartridge space etc. Setting an appropriate bit also disables the new 16-bit wide RAM expansion and instead brings in the standard, 8-bit wide memory expansion, if available.

Thus I have two 32 K RAM expansions in the machine at the same time, one fast 16-bit internal for normal use and one slower 8-bit wide, that can be used for buffers in assembly programs, emulate a RAM disk or whatever you need. Or you can load a program there, if it relies on timing with normal memory to run properly.

 

Since the TI frequently use writing to ROM areas for memory mapped ports, bank switching and similar, I didn't implement write through, though. To efficiently copy ROM to RAM, I can do like this:

  • Enable RAM at 4000H.
  • Copy 8 K from 0000H to 4000H.
  • Enable RAM at 0000H.
  • Copy 8 K from 4000H to 0000H.
  • Disable RAM at 4000H (to free up DSR access again).

Now the operating system at 0000H is in RAM, and can be modified as you like.

 

I also added some hardware which causes a one cylce wait state when accessing the VDP. That too is controlled with a CRU bit, since it's not needed for software which does have that extra NOP which is recommended by TI. But in some cases, with normal memory expansion, such a NOP isn't needed. Thus some programs don't have it, but then fails when you run from faster memory.



#28 marc.hull OFFLINE  

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Posted Fri Apr 21, 2017 7:42 PM

I would really like to see your schematic one day as well as your cut list for the traces on the mobo. Very interested in this.

#29 Willsy OFFLINE  

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Posted Sat Apr 22, 2017 12:34 AM

Yes. This would be an awesome mod. Really open up the machine.

#30 apersson850 OFFLINE  

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Posted Sat Apr 22, 2017 2:29 PM

I doubt I have a cut list for the traces, but I do have some schematics, somewhere.

Meanwhile, the last three pictures in this album shows the internal modification. Only the last one also contains the VDP access wait state logic.

As you can see I never made any PCB, but the modification is completely self-contained inside the original metallic screen inside the 99/4A. Thus you could for example run assembly programs without the PEB, if you loaded from cassette. Like you could with Mini Memory, but here you could also have Extended BASIC plugged in, for example. I did a demo of Forth on a seemingly unexpanded console, with cassette tape recorder connected only, at a meeting in Sweden once.

 

To begin with, I installed the modification with one single bit toggling all 32 K RAM expansion, and individual bits toggling the other 8 K sections. But I realized that it was smarter to be able to handle the 8 K RAM and the 24 K RAM expansion areas (2000H-3FFFH and A000H-FFFFH) separately, so I modified the logic to Control them by two different bits. Since I also need a bit for the VDP wait state generation control, and I have eight bits in my latch, I couldn't spend one bit per 8 K memory bank. But usually it makes sense to consider the 24 K RAM part as one single section anyway.

 

Forgive me if I have made some error. I did this modification in the 1980's.

 

Together with the 56 K Maximem universal module, this additional 64 K RAM memory and some memory on my additional home made wire wrap PEB cards, I simulate a RAM-disk for the p-system. I remember that compiling a Pascal program was done in about half the time when the compiler was in RAM all the time, due to the extensive segmentation of that program.

Later additional memory devices with a lot more memory has been designed, but 176 K RAM was quite a lot in 1985. The fact that my design co-exists with the standard 32 K RAM expansion made a difference.

I used 400H as the base address for the CRU bits used to swap in/out RAM segments.


Edited by apersson850, Sat Apr 22, 2017 2:41 PM.


#31 Willsy OFFLINE  

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Posted Sat Apr 22, 2017 3:25 PM

*** WARNING WARNING WARNING ***
VIEWERS ARE HEREBY ADVISED THAT THE ABOVE LINK FEATURES PHOTOS OF A SILVER TI-99/4A CONSOLE FITTED WITH A BEIGE KEYBOARD. YES YOU READ THAT RIGHT FOLKS. VIEWER DISCRETION IS ADVISED. THIS WEBSITE SHALL NOT BE HELD RESPONSIBLE FOR FEELINGS OF OUTRAGE, SORROW, SHOCK OR DISTRESS.
YOU HAVE BEEN WARNED.

We now return you to your normal content.

Thank you.

#32 apersson850 OFFLINE  

apersson850

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Posted Sun Apr 23, 2017 1:58 AM

You better behave, or I'll show you a picture of the other one too. It looks the same... :P 



#33 Opry99er OFFLINE  

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Posted Sun Apr 23, 2017 7:31 AM

Damn... actually, I don't mind the look of that at all, surprisingly...

#34 TheBF OFFLINE  

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Posted Wed Apr 26, 2017 7:16 AM

Even though I haven't done much to improve the interpreter,  TIMXT now seems to be stable at 57.6K with the wired connections shown in the screenshot.  ;)

 

Did you incorporate the power of 2 sized buffer concept to get that the speed?



#35 InsaneMultitasker OFFLINE  

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Posted Wed Apr 26, 2017 9:27 AM

 

Did you incorporate the power of 2 sized buffer concept to get that the speed?

In this case, no. I was being coy, trying not to say too much because what is shown in the picture is TIMXT running from the ubergrom cartridge UART.   Unlike the 9902-based RS232, the UART has a multiple-byte FIFO, which makes incoming data capture a bit simpler.  I still plan to implement the power of 2 buffer in both versions, as soon as I have the time to do so.  :)



#36 TheBF OFFLINE  

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Posted Thu Apr 27, 2017 9:50 AM

In this case, no. I was being coy, trying not to say too much because what is shown in the picture is TIMXT running from the ubergrom cartridge UART.   Unlike the 9902-based RS232, the UART has a multiple-byte FIFO, which makes incoming data capture a bit simpler.  I still plan to implement the power of 2 buffer in both versions, as soon as I have the time to do so.  :)

 

Ahh.... hardware FIFOs are the bomb. Make serial communication sooo much easier. Almost like cheating to us old-timers.

 

Thanks for the update

 

B







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