Since STST doesn't do a read before write, would clearing CPU RAM using STST overrun the VDP?
(Clearing VDP RAM) Absolutely and by a long shot. You need 8 microseconds between writes, that's 24 cycles. Our assertions that you can't overrun the VDP were based on moving data. STST is only 8 cycles, targeting the VDP would make it 12. Even CLR at 10 cycles is too fast - targeting the VDP makes it only 18.
Of course you can use it while the VDP is in blank - either vertical blank or display blanking enabled.
(edit: the fastest data move, assuming you could change a register dynamically, MOVB R1,*R2 is 14 for the opcode, 4 for the indirect, and 8 for the wait states, making 26 cycles. More commonly it'd be MOVB *R1+,*R2, which adds another 8 cycles for the indirect auto-increment and makes 34 cycles. But you could use the former for a direct-to-VDP clear, if there was a reason that was useful (or you had custom hardware, which was something I wanted to try
Edited by Tursi, Thu Mar 10, 2016 3:57 AM.