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32k expansion for the side port - released

32k sidecar memory

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#1 jedimatt42 OFFLINE  

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Posted Mon Jul 4, 2016 7:19 PM

32k sideport memory card: 

 

Product started shipping October of 2016

Sold through Arcadeshopper.com

   https://www.arcadesh...=0&sort=nameAsc

My personal project page:

   http://ti994a.cwfk.net/32k.html 

 

Available in assembled and tested form, or kit form.

 

See my project page for a video detailing how to assemble (if you are thinking about the kit form)

 

-M@

 

------- Original-ish 1st Post ----------

 

I feel we need a simple 32k expansion that slaps onto the side of the 4a, or side of the speech synthesizer... So I've been trying to build one. 
 
There are a number of new cartridges that require the 32k memory expansion to function. And with the Flash ROM 99 EA5 conversion craze, a console with 32k on the side can suddenly play a much larger library of classic and new TI software titles. 
 
My intent is to build and offer finished product. I envision a vertical board about 3" high by 4" deep, chips to the right, edge connector to the left. And a jumper for external or internal power. 
 
--
 
I've started with the circuit on TI TECH PAGES, under http://www.unige.ch/...ti99/mem32k.htm, scroll down to do-it-yourself-card. 
 
This circuit maps logically to what Tursi describes in http://www.harmlessl.../TI 32k Mod.pdf from the best of my ability to tell. 
 
Of course, I'm not in a PE-Box with this, so I have no RDBENA to worry about. So I've reduced the circuit, using the remaining 3 single line buffers in the 74LS125 to buffer MENEN, WE, and DBIN, instead of the 3rd 74LS244. 
 
I believe I have all of the addressing correct, and can actually see the LED in the circuit activate when and only when I address memory in the expansion address ranges. However, I am having a real difficult time with the memory chip, and the data bus buffer 74LS245.   Maybe some of you with more experience can spot what I'm doing wrong?  It seems as though I'm stuck in high-impedance mode on the data bus buffer.
 
It is not shown in this schematic, but I've got 0.1uf caps across Vcc and Vss on all of the chips. And I'm driving the board off of an external 5v regulated supply. 
 
I'm using a 62256 SRAM and not either the 55256 Theiry called for, or the CY7C199 from Tursi's circuit. They appear to be pinout compatible with the 55256. The address lines are numbered different in the CY7C199.  
 
Here is my first schematic: 
Attached File  SideCar32kSchematic.jpg   463.42KB   27 downloads
 
PDF if you want to look more closely: 
Attached File  32k-side-car-schematic.pdf   70.84KB   38 downloads
 
And a picture of all my jumper wires in use for fun:
Attached File  IMG_20160703_171936.jpg   168.68KB   25 downloads
 
I now believe paying $30 for the 4k of ram in my mini memory cartridge was worth it, since it came with Easy Bug :)
 
-M@

----

This post has the final schematic I designed the boards off of:

http://atariage.com/...dpost&p=3590849

-M@



#2 Opry99er OFFLINE  

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Posted Mon Jul 4, 2016 7:25 PM

:) A noble venture!!

#3 --- Ω --- OFFLINE  

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Posted Mon Jul 4, 2016 7:46 PM

This is an EXCELLENT idea/project! :thumbsup:   Like you said, this will go great with the FlashROM 99.  Many people who only want to play games will probably scarf these up as it'll make entry, or re-entry into the TI world affordable and painless.  From the looks of the schematic it should be easy enough to shrink down.  I think you'll make a lot of people very happy.

 

msg-35324-0-17776900-1467686561_thumb.pn



#4 Tursi OFFLINE  

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Posted Mon Jul 4, 2016 7:53 PM

On a quick look, and I may be mis-reading your schematic, but it looks like your memory expansion select signal after the quad AND gate is active-high, but you are feeding it into an active low !CS on the RAM chip (and is the 245's CE active high or low? I didn't look up the datasheets).

I can't check everything right now, but that's one that jumps out at me. Write out a truth table for each of your generated signals and make sure you're getting the signal you meant for. :)

I also kind of wondered, not that it's wrong, but why invert MEMEN just to feed it into the '138 when the 138 has both active high and active low enable lines? Why not just route it to the appropriate enable?

#5 jedimatt42 OFFLINE  

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Posted Tue Jul 5, 2016 12:09 AM

Thanks.  

 

I believe the outputs of the '138 are inverted, so when one of the expansion's 4 banks is selected, the output of the quad AND becomes active-low, and then yes, the CS on the RAM is active low...  as is the CE on the '245. The templates sadly use two different notations.  

 

And MEMEN isn't inverted, it too is active-low so it goes to an inverted enable pin 4(E1) on the '138.  It travels through a single buffer gate on the '125, which is just me being naive, and buffering everything.

 

Since I'm not actually spreading the signal of anything but address lines A0-A2, it seems to me that I could drop the '244s and '245, and buffer just those 3 address lines through the '21, and run all the other address, signal, and data bus lines direct to their single destinations on the board.   Is that crazy?

 

Testing through the truth table is a strong idea.  I tested through a subset of it, but now I have doubts that I had MEMEN correct. 

 

-M@



#6 ralphb OFFLINE  

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Posted Tue Jul 5, 2016 12:44 AM

You have the SRAM OE* connected to GND ...  Wouldn't OE* low and WE* low at the same time be undefined?



#7 Stuart OFFLINE  

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Posted Tue Jul 5, 2016 2:13 AM

As this is going direct on the side port, I think you should be able to get rid of all the buffers down the left hand side (everything is buffered in the console anyway). Connect the RAM /OE to /CS.

 

With your current problem, I think the logic of DBIN is wrong wrt how you've got the LS245 wired. When DBIN is high, the processor is reading data, but according to the LS245 spec sheet it is transferring data from A to B, which is the wrong direction. You'd need to either invert DBIN, or swap the signals on the LS245 to the opposite sides. (Thierry on his web page cunningly doesn't show which sides the data bus is connected to.)

 

Does your LED have a built-in current limiting resistor?


Edited by Stuart, Tue Jul 5, 2016 2:35 AM.


#8 mizapf OFFLINE  

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Posted Tue Jul 5, 2016 2:22 AM

Connect the RAM /OE to /CS.

 

Are you sure? I'd expect this to work for a ROM, but when you write to the RAM you don't want to get a collision of incoming and outgoing data.



#9 Stuart OFFLINE  

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Posted Tue Jul 5, 2016 3:20 AM

 

Are you sure? I'd expect this to work for a ROM, but when you write to the RAM you don't want to get a collision of incoming and outgoing data.

 

Yes, it's a valid use-case (according to the spec sheets), subject to timing constraints. As the /WE pulse is within the period that /CS and /OE are low (controlled by /MEMEN), then it seems to be OK (/WE being low takes precedence over the state of /OE). That's how I've got my in-console 32K RAM arranged, and that works OK. http://www.stuartcon...emory_expansion


Edited by Stuart, Tue Jul 5, 2016 3:36 AM.


#10 mizapf OFFLINE  

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Posted Tue Jul 5, 2016 4:03 AM

Ah, OK ... I checked the schematics, the circuit I had in mind actually ORs the lines /CS, /OE, and ¬/WE line internally before leading them to the tristate outputs, so an  asserted /WE (=0) means the same as a not asserted /OE (=1).


Edited by mizapf, Tue Jul 5, 2016 4:31 AM.


#11 ti99iuc OFFLINE  

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Posted Tue Jul 5, 2016 5:07 AM

Could be hard to add the 32Kb into the Speech case ? there is a lot of free space into it :P 

 

so we could have speech and 32K into the same sidecar box :)

 

i'am dreaming ?



#12 Stuart OFFLINE  

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Posted Tue Jul 5, 2016 5:33 AM

Could be hard to add the 32Kb into the Speech case ? there is a lot of free space into it :P

 

so we could have speech and 32K into the same sidecar box :)

 

i'am dreaming ?

 

Should be fairly easy to do, but it would be a DIY project rather than a standalone product you can buy/sell, which is what I think Matt is aiming for.



#13 00WReX OFFLINE  

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Posted Tue Jul 5, 2016 5:33 AM

OK, nothing useful to add other than...please put my name down for one when they are ready ;)

 

Cheers,

Shane



#14 jedimatt42 OFFLINE  

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Posted Tue Jul 5, 2016 5:39 AM

You all rock!

You have the SRAM OE* connected to GND ...  Wouldn't OE* low and WE* low at the same time be undefined?

 
I had doubts about this, but the datasheet for the 62256 actually defines that state as a write state.

 

As this is going direct on the side port, I think you should be able to get rid of all the buffers down the left hand side (everything is buffered in the console anyway). Connect the RAM /OE to /CS.
 
With your current problem, I think the logic of DBIN is wrong wrt how you've got the LS245 wired. When DBIN is high, the processor is reading data, but according to the LS245 spec sheet it is transferring data from A to B, which is the wrong direction. You'd need to either invert DBIN, or swap the signals on the LS245 to the opposite sides. (Thierry on his web page cunningly doesn't show which sides the data bus is connected to.)
 
Does your LED have a built-in current limiting resistor?


:) I broke two LEDs as I built up starting from the LED. I'll update the schematic before I open source this.

Ah, DBIN and A->B on the the '245... I have high hopes that swapping the inputs around should solve the problem I'm seeing. I'll give this a shot. Once that works, I'll try removing all the buffering...

---

thanks!
-M@

#15 jedimatt42 OFFLINE  

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Posted Tue Jul 5, 2016 5:49 AM

Should be fairly easy to do, but it would be a DIY project rather than a standalone product you can buy/sell, which is what I think Matt is aiming for.


Yep, I want 32k for every 4a.

-M@

#16 mizapf OFFLINE  

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Posted Tue Jul 5, 2016 5:51 AM

I had doubts about this, but the datasheet for the 62256 actually defines that state as a write state.

 

Which is consistent with what I found out; the /OE and /WE are internally combined. Output (i.e. CPU read) is only activated for /WE=1, /CS=0, /OE=0.



#17 jedimatt42 OFFLINE  

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Posted Tue Jul 5, 2016 9:11 AM

I didn't have time for a full experiment before work, but I did a quick swap on one data line around the A and B sides of the '245, and I am able to change a bit in Easy Bug, read it, and clear it.

So epic progress! Thanks!

-M@

#18 Stuart OFFLINE  

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Posted Tue Jul 5, 2016 9:24 AM

;-)  Good luck with the other 7 bits.



#19 --- Ω --- OFFLINE  

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Posted Tue Jul 5, 2016 9:45 AM

 

My intent is to build and offer finished product.

 

 

Yep, I want 32k for every 4a.

 

 I like the fact that you plan to cover both bases.  You will certainly get them into more hands with a finished product because some people don't have a soldering iron or even know how to solder, so they don't want to risk wasting their money by butchering a kit.  Others can be too busy to take on another project, but would like to play a game or two now and then when they get the chance.  By offering a kit too, the tinkering types get to come out and play!   Yep that'll get 32K in every 4A possible.



#20 Iwantgames:) OFFLINE  

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Posted Tue Jul 5, 2016 4:52 PM

I'd take one when its done too :)

#21 marc.hull OFFLINE  

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Posted Tue Jul 5, 2016 7:24 PM

Good project Jedi. Are you going to make it pass thru ?

I ran into the same issue on Jim's proto board that uses DBIN as the direction signal on the 245. More than once I reported a design bug to him never considering it was wired B side to PEB and A side to the card guts because of the IC's physical layout.

Crow was eaten with a little salt and lime😄.

#22 jedimatt42 OFFLINE  

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Posted Tue Jul 5, 2016 10:05 PM

Good project Jedi. Are you going to make it pass thru ?

I ran into the same issue on Jim's proto board that uses DBIN as the direction signal on the 245. More than once I reported a design bug to him never considering it was wired B side to PEB and A side to the card guts because of the IC's physical layout.

Crow was eaten with a little salt and lime.

 

Yep DBIN is a little counter intuitive to me, mainly because I don't know how to use the mnemonic in a sentance... As a CPU when I say DBIN I want data in...  but what's the 'B'   ?   And of course, I'm focused on the '245 chip, and the board, so 'in' seems like output from the cpu input into the board.

 

I managed to get the rest of the 7 bits wired, and played a good game of parsec off of the flash rom 99 cartridge, which is an EA5 loader version.

 

As for pass thru, I don't want to close the door. But from a use case point of view, if you have a PEB, you should get a SAMS, or you already have a TI 32k. So, this thing can target the end of the TI chain, if you have a picnic table setup and sidecar floppies and serial and whatnot...

 

But I am thinking of adding a pass thru headers so future boards could be stacked off of it.  Or, an inventive person could print an edge card to IDC adapter. 44pin IDC connectors don't seem to be common anymore... I think they were a harddrive standard at one point... so I may look for a layout that supports a popular IDC connector. I don't feel compelled to keep the right hand side compatible with existing peripherals. 

 

So, the thing works mostly :)  Next is to peel back unnecessary complexity.  Also, I consistently get an error at >COFE using the Corcomp diagnostics on the XB2.7 cartridge. But if I go into Easy Bug, I can read and write to that address reliably.   I don't know if I blame that on that rats nest of jumper wires in post #1... I think I do. :)  

 

-M@



#23 Stuart OFFLINE  

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Posted Wed Jul 6, 2016 2:08 AM

 

As a CPU when I say DBIN I want data in...  but what's the 'B'   ?  

 

 

'B' is for 'Bus'. 'Data Bus In'.



#24 jedimatt42 OFFLINE  

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Posted Thu Jul 7, 2016 12:06 AM

I gave it a shot today without the buffers, but it behaved very badly... manually, not connected to the TI, I can walk through the range of values A0-A2 with memen grounded, and get the CS output I want..  But connected to the 4a, it just seems to respond to all address ranges.

 

Anyway, I'll have to strip it down, and try again.  I may try just buffering A0-A2 two see if that fixes the selection.  

 

I'm interested in being able to run with 3 less chips.. not so much because of the buffer chips cost, but because the pcboard can get to be significantly cheaper the smaller it is. 

 

Edit: ( I found the TI-99/4a Console Technical Data pdf on mainbyte...  A Big thanks to the owner of that site! ) 

 

-M@



#25 Stuart OFFLINE  

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Posted Thu Jul 7, 2016 2:37 AM

As you've been rewiring, make sure you've still got address bus A0-A2 reversed when connecting to the LS138 A0-A2, like on your original schematic. Easy to get that wrong, and it would give strange results.







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