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32k expansion for the side port - released

32k sidecar memory

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#76 retroclouds OFFLINE  

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Posted Thu Aug 18, 2016 10:17 PM

would be cool if, in addition to the 32k ram , the board could include a programmable timer that generates a load interrupt signal. See some possibilities for a task scheduler that way.

#77 Opry99er OFFLINE  

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Posted Thu Aug 18, 2016 10:51 PM

My speech synth has a load interrupt button on it. :D


Richard Lauhead from the MSP UG did the mod.

#78 OLD CS1 OFFLINE  

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Posted Fri Aug 19, 2016 6:29 AM

My speech synth has a load interrupt button on it. :D

 

Can you hit that 60 times a second? ;)



#79 jedimatt42 OFFLINE  

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Posted Fri Aug 19, 2016 10:56 AM

i can see me buying a couple of these when they are out!


I clearly need a bigger house so I can have need for even one.

-M@

#80 Opry99er OFFLINE  

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Posted Fri Aug 19, 2016 11:19 AM

 
Can you hit that 60 times a second? ;)



I suppose this would depend on a few factors... ;)

I do live in Tennessee and could probably scrounge up some meth... My wife is a coffee drinker, so I have access to that.

I am guessing without chemical modification, I could hit the button 7-8 times in a second.

#81 jedimatt42 OFFLINE  

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Posted Fri Aug 19, 2016 12:07 PM

would be cool if, in addition to the 32k ram , the board could include a programmable timer that generates a load interrupt signal. See some possibilities for a task scheduler that way.

 

How about a slow-motion option? poking the READY pin so you can slow down your games... 

 

Actually, all of that is out of scope... I believe in single-responsibility principles of design. I am working on a layout that includes headers for daughterboards. You could add whatever you want that way. 

 

-M@



#82 Tursi OFFLINE  

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Posted Fri Aug 19, 2016 12:12 PM

I suppose this would depend on a few factors... ;)

I do live in Tennessee and could probably scrounge up some meth... My wife is a coffee drinker, so I have access to that.

I am guessing without chemical modification, I could hit the button 7-8 times in a second.

 

Well, if it doesn't have a debounce circuit, you could take advantage of mechanical contact bounce for a few more rapid hits... mind you it's pretty hard to control the frequency of the input. ;)



#83 JamesD OFFLINE  

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Posted Fri Aug 19, 2016 12:58 PM

would be cool if, in addition to the 32k ram , the board could include a programmable timer that generates a load interrupt signal. See some possibilities for a task scheduler that way.

Playing back sound samples and 1 bit music would certainly benefit from a higher interrupt rate.
As I said in another thread, the one in the CoCo 3 would be worth a look and it's not difficult to implement.

A task scheduler can run off of a vertical blank interrupt. 



#84 retroclouds OFFLINE  

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Posted Sun Aug 21, 2016 3:06 AM

Playing back sound samples and 1 bit music would certainly benefit from a higher interrupt rate.
As I said in another thread, the one in the CoCo 3 would be worth a look and it's not difficult to implement.

A task scheduler can run off of a vertical blank interrupt. 

 

I'm aware it's possible to use the vertical blank interrupt for that. I've already done a task scheduler on the TI-99/4A using that approach (spectra2 game library).

But I'd like to try my hands on implementing some form of preemptive task scheduling; timed load interrupts would fit that perfectly. Also a nice benefit would be the higher interrupt rate. 

 

That could possibly also be accomplished using the TMS9901 as a timer. There was a discussion about that a few years ago http://atariage.com/...901-as-a-timer/



#85 jedimatt42 OFFLINE  

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Posted Tue Aug 30, 2016 12:57 PM

In attempting to make the pcboard layout small, the address lines from the TI to the SRAM chip are the biggest pain. So i am thinking order of an address line doesn't matter to RAM like it does to ROM. Except of course those that are about the highmem/lowmem mapping.

Am I crazy, or correct?

-M@

#86 Stuart OFFLINE  

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Posted Tue Aug 30, 2016 4:04 PM

In attempting to make the pcboard layout small, the address lines from the TI to the SRAM chip are the biggest pain. So i am thinking order of an address line doesn't matter to RAM like it does to ROM. Except of course those that are about the highmem/lowmem mapping.

Am I crazy, or correct?

-M@

 

Correct. Ditto for the data lines as well.



#87 JamesD OFFLINE  

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Posted Tue Aug 30, 2016 4:22 PM

 

I'm aware it's possible to use the vertical blank interrupt for that. I've already done a task scheduler on the TI-99/4A using that approach (spectra2 game library).

But I'd like to try my hands on implementing some form of preemptive task scheduling; timed load interrupts would fit that perfectly. Also a nice benefit would be the higher interrupt rate. 

 

That could possibly also be accomplished using the TMS9901 as a timer. There was a discussion about that a few years ago http://atariage.com/...901-as-a-timer/

Just keep a counter of vertical blank interrupts.   
The Amiga does this.  You can set how many "jiffies" between task switches and that's just that counter.



#88 jedimatt42 OFFLINE  

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Posted Tue Aug 30, 2016 4:28 PM

I'm officially and politely asking now that task scheduler discussions move to a new thread.  It will make it easier for people to find your discussion as well. 

 

-M@



#89 Willsy OFFLINE  

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Posted Wed Aug 31, 2016 3:38 AM

 

Correct. Ditto for the data lines as well.

Aye. It's only important for ROM.



#90 Lee Stewart OFFLINE  

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Posted Wed Aug 31, 2016 6:07 AM

In attempting to make the pcboard layout small, the address lines from the TI to the SRAM chip are the biggest pain. So i am thinking order of an address line doesn't matter to RAM like it does to ROM. Except of course those that are about the highmem/lowmem mapping.

Am I crazy, or correct?

-M@

 

I don't understand the implied question in your opening paragraph.

 

...lee



#91 jedimatt42 OFFLINE  

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Posted Wed Aug 31, 2016 8:35 AM

I don't understand the implied question in your opening paragraph.
 
...lee


The question is: can I swap address lines 5 and 6 between the TI and the SRAM chip?

With a prom, there must be a contract defining how the lines are used so that the chip can interface with multiple devices, namely the programmer device and the consuming device.

But with the sram, and no battery and removability goals, there is only one device to make a contract with.

So it is fine to swap, swivel and shuffle the data and address lines.

My first board posted earlier was about 4"x3" , armed with this knowledge and less chips, my layout is now 3"x2". This cuts the cost of the most expensive component in half since you typically pay by the square inch.

----

Speaking of less chips, I have eliminated the buffers for the address lines and control signals but kept the buffers for the data lines. This passes memory tests on the prototype, where not using the buffer back to the TI typically failed memory tests.

So it is down to the following 4 ics:
SRAM,
Bidirectional data line buffer
3 to 8 bit decoder
Double quad-AND gate

The LED is controlled with a discrete pnp transistor.

So I feel done enough trying to reduce waste from the design.

-M@

#92 --- Ω --- OFFLINE  

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Posted Wed Aug 31, 2016 8:57 AM

That is neat!  I'm glad you included a little LED in the design to jazz things up a little.

I cannot wait to get my hands one.  I'm building another (smaller) TI system up and it NEEDS  this little device.

 

The size you mentioned seems rather nice.  Once this thing is completed and someone designs a 3D printed case for it, they'll be flying out the door.  I can see many more people getting into the TI with a combo of your memory expansion married with the FR99.



#93 Sinphaltimus OFFLINE  

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Posted Wed Aug 31, 2016 9:04 AM

I need this as well. I'm not waiting on no cases. You say when.

This, and the Vampire II board for my Amiga 500 (it's at about the same stage of development) and I'll be set. *THUD*

Edited by Sinphaltimus, Wed Aug 31, 2016 9:07 AM.


#94 Willsy OFFLINE  

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Posted Wed Aug 31, 2016 10:57 AM

Have you got a schematic?

#95 Tursi OFFLINE  

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Posted Wed Aug 31, 2016 11:23 AM

You can normally swizzle both address and data lines to a RAM chip, yes. All a RAM cares is that each address points to a unique cell, the order of the cells or the bits doesn't matter. :)



#96 jedimatt42 OFFLINE  

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Posted Wed Aug 31, 2016 11:59 AM

Have you got a schematic?

 

I have 2 schematics, and neither are exactly what I've designed on the pcboard.

Next steps:

  update the schematic to match what I'm building

  build that exactly on the breadboard again

  check the pcboard layout against the schematic

  wait for the power jacks to arrive so I can verify the physical layout

  get OSHPark to print me a sample - wait 12 days

  build the sample

  cross my fingers

  test the built sample

  order parts and boards in greater quantity

  wait

  assemble

  test

  distribute

 

Of course things could go horribly wrong.   

 

-M@



#97 Ksarul OFFLINE  

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Posted Wed Aug 31, 2016 5:42 PM

But it is a really fun ride, @Matt--and when you are done you'll have a project to be proud of, one that really serves a community need.  :)



#98 jedimatt42 OFFLINE  

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Posted Wed Aug 31, 2016 6:01 PM

But it is a really fun ride, @Matt--and when you are done you'll have a project to be proud of, one that really serves a community need.  :)

 

It is totally fun!  This little board is cause for learning so many fundamentals.  When I was 11, the TI made me decide I wanted to go to college and learn to do this sort of thing... design ICs actually. But then I started programming classes in high school, decided I didn't need to learn to mess with hardware. ( Which I would still say is true, based on the word 'need' ) But learning to mess with hardware is so much more rewarding/tangible right now than the last 20 years of bits on disk.   I do want to settle down for a while and really do some game writing on the TI and Geneve once this board is rolling out.  But who knows. It is all hobby heaven. 

 

-M@



#99 arcadeshopper ONLINE  

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Posted Thu Sep 1, 2016 11:41 AM

Can't wait to see/try it! Great work and thanks for sharing the details :) 

 

Greg



#100 Sinphaltimus OFFLINE  

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Posted Thu Sep 1, 2016 12:13 PM

I may have gotten confused with several projects around here.

I want to be clear, this is a 32k ram expansion for the side port that replaces the need for 32k in a PEB or replaces the 32k internal ram mod correct?

No other bells whistles features or doodads right? An amazing accomplishment for sure, just trying to set my expectations properly, it can not; for instance, core a apple.

Edited by Sinphaltimus, Thu Sep 1, 2016 12:14 PM.






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