ricortes Posted January 14, 2017 Share Posted January 14, 2017 Comparing the raise time on the above waveforms is a bit misleading because they have different amplitude. You can see that the upper waveform, that corresponds to the input of the 74LS08, has a much higher amplitude than the bottom waveform. Should be in the order of 5V vs 3V. But what matters is the rise time to somewhere around 2V that would switch any TTL compatible component receiving the signal. If you try to compare then, the rise time from 0V to 2V, the difference between both waveforms is not that dramatic. Still probably a bit shorter on the lower waveform, but not nearly that much. Note that Mike is more concerned about the propagation delay than about the rise time. OK, I was just concerned about best case/worse case scenarios where you could get ttl switching at ~.8 V and CMOS switching at 2.5 V tossed in on top of gate propagation delays. It implies some form of squaring up the PH2 line & propagation delays are both important. Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 21, 2017 Author Share Posted January 21, 2017 (edited) Test Results with 74AC08 AND Gate substituted for original 74LS08 Device... As expected using a much faster device created major over/undershoot of the buffered PH2 output signal. However adding a bit of resistance in series cleaned up the waveform very nicely. And even with the added resistance in the path, voltage drop was minor, and slew rate appears only mildly affected. By using this faster device, probagation delay has been reduced from the original LS device's 29 ns down to 10 ns. Seems like this should do the trick - Michael Edited January 21, 2017 by mytekcontrols 1 Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 21, 2017 Author Share Posted January 21, 2017 (edited) Changed from a 47 ohm series resistor to a 33 ohm resistor, and eliminated rounding on front edge. Slight overshoot as a result, but very minimal. Also falling edge looks steeper. I think this is a good compromise. - Michael EDIT: These results are still based on using a 74AC08 device in place of the original 74LS08. Edited January 21, 2017 by mytekcontrols 3 Quote Link to comment Share on other sites More sharing options...
+bob1200xl Posted January 21, 2017 Share Posted January 21, 2017 You might want to keep that 47 ohm resistor handy. The best value of the series resistor is determined by the effective impedance of the load on the B02 pin, which you do not have connected, yet. At the end of the day, I just wire in my 100 ohm pot and adjust to suit. Then, select the closest 5% resistor. The objective of this whole exercise is to match the source impedance at the '08 output pin to the load impedance at the end of the driven net, values that we really don't know. This is the 02 clock. It would be interesting to see how plugging in a cartridge will affect the waveforms. Or, installing a PBI device. Bob 2 Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 21, 2017 Author Share Posted January 21, 2017 (edited) Hi Bob I was using a SIDE2 which is a PBI device which plugs into the cart port (doesn't need the ECI provided signals). I unplugged it, and observed no discernible change. Then I tried a Mac65, Basic XL, Assembler/Editor, Missile Command, Star Raiders, and a UNO Carts, with all of them working fine and not changing the waveform. Then just for grins, R-Time8 with BASIC XL piggybacked on top --- still looked the same. So then I moved the probe over to the PH2 input on the U1MB board which is far away from the 74AC08 chip and fed by a 5" piece of wire from a different point. There I could see that the over/undershoot had increased (140 mv peaks above/below). By then switching to a 47 ohm resistor I cut this nearly in half (80 mv peaks above/below). And when going with a 68 ohm resistor the over/undershoot is virtually gone. Unfortunately I don't nave a BB to test on the PBI, which would be interesting since I've heard it can be kind of cranky. Looks like 68 ohms would be a better candidate, enough to tame the over/undershoot to acceptable levels, while not doing terrible things to the signal's waveform. Interestingly the rounding of the edges is much more pronounced in the signal coming straight out of the 74AC08 buffer, but not visible when looking at where PH2 comes into the U1MB. BTW, in that 3rd O-Scope photo I had moved the probe's ground lead over to the U1MB, notice the increase in ground noise. - Michael Edited January 21, 2017 by mytekcontrols 3 Quote Link to comment Share on other sites More sharing options...
Blake Posted January 22, 2017 Share Posted January 22, 2017 Just a crazy thought... but, what if you piggy-backed the faster 74 onto the original 74, would that not speed things up, without loosing compatability, understandably, it would seem like there were "two minds at work" but wouldn't whomever gets there too slow in certain instances, just be ignored since their signal is just catching up to the same logic level, that has already been established by the faster of the two, essentially being ignored for being too slow to propagate, and then be recognized for having the right fall-time when it matters, or just throw in the 68 resistor to keep the fall times in sync? Like I said, just a crazy thought since you kinda have to keep a 74 in the mix either way. Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 22, 2017 Author Share Posted January 22, 2017 Just a crazy thought... but, what if you piggy-backed the faster 74 onto the original 74, would that not speed things up, without loosing compatability, understandably, it would seem like there were "two minds at work" but wouldn't whomever gets there too slow in certain instances, just be ignored since their signal is just catching up to the same logic level, that has already been established by the faster of the two, essentially being ignored for being too slow to propagate, and then be recognized for having the right fall-time when it matters, or just throw in the 68 resistor to keep the fall times in sync? Like I said, just a crazy thought since you kinda have to keep a 74 in the mix either way. I think there would be a fight, since they are from two entirely different families TTL vs HCMOS. But it would make for an interesting experiment - Michael Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 22, 2017 Author Share Posted January 22, 2017 The objective of this whole exercise is to match the source impedance at the '08 output pin to the load impedance at the end of the driven net, values that we really don't know. This is the 02 clock. It would be interesting to see how plugging in a cartridge will affect the waveforms. Or, installing a PBI device. Bob Not knowing what the downstream impedance will look like is the problem with the resistor in series approach, because it's going to vary depending upon what is hanging off of the bus. So maybe a better approach would be to use a zener diode to limit the voltage excursion, so that it can't get beyond the 5 V threshold. Although without trying it, I don't know what the side effects would be, and I'm sure there would be some. - Michael Quote Link to comment Share on other sites More sharing options...
+bob1200xl Posted January 22, 2017 Share Posted January 22, 2017 A lot of data gets latched on the falling edge of PH02, rather than the rising edge. So, you need to pay attention to both clock phases. A signal like !CCTL doesn't have any load if you don't have a cartridge plugged in, which is why you might want to scope it in both states. Zeners will probably not be fast enough and/or have too much capacitance for high clock speeds. The resistors will work, you just have to find their value empirically. Place the resistors as close to the source pin as possible. ...and cross your fingers... Bob 3 Quote Link to comment Share on other sites More sharing options...
ricortes Posted January 22, 2017 Share Posted January 22, 2017 Is diode clamping out of the question because of forward voltage? I'm a reductionist at heart so your one resistor solutions looks better then two small signal diode clamp. 2 Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 22, 2017 Author Share Posted January 22, 2017 The resistors will work, you just have to find their value empirically. Place the resistors as close to the source pin as possible. ...and cross your fingers... Yeah as I've already seen, any resistance is better than none when it comes to controlling the over/undershoot. So even if I don't obtain perfection for every situation, it should still be good an approximated value. I'm a reductionist at heart so your one resistor solutions looks better then two small signal diode clamp. I'm with you on the 'reductionist' aspect - Michael 1 Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 23, 2017 Author Share Posted January 23, 2017 So next on the agenda, will be to scope out the Φ0 signal coming from Antic over to the CPU. In most of the Atari iterations, this signal is also buffered by another AND gate. Since the Φ0 signal is not distributed to anything else, I am curious as to why this was done. Part of me suspects that it has to do with the delayed buffered Φ2 signal, and perhaps this an attempt to bring the timing back into alignment. Any other theories? - Michael Quote Link to comment Share on other sites More sharing options...
+bob1200xl Posted January 23, 2017 Share Posted January 23, 2017 I would guess that the 02 clock is derived from the PH00 input, since nothing else seems to be available to act as the master clock. If that is true, moving PH00 around would also move PH02. By the same logic, PH00 seems to be derived from OSC, so delaying PH00 would necessarily change the relationship between PH00 and OSC. The result is that it changes the timing between OSC and PH02. Probably to latch graphics data with PH02? Nobody else uses OSC. Bob Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 23, 2017 Author Share Posted January 23, 2017 (edited) I would guess that the 02 clock is derived from the PH00 input, since nothing else seems to be available to act as the master clock. If that is true, moving PH00 around would also move PH02. By the same logic, PH00 seems to be derived from OSC, so delaying PH00 would necessarily change the relationship between PH00 and OSC. The result is that it changes the timing between OSC and PH02. Probably to latch graphics data with PH02? Nobody else uses OSC. Bob Yeah stupid me, of course any delay added to the Φ0 input (which is the CPU master clock) would inherently delay the Φ2 output. So if you also add in the fact that they always buffer Φ2, it's like they are doubling the delay in reference to OSC (3.58 Mhz in NTSC version). If this were only consistent across the series I might understand it, but it is not. The XEGS does not touch the Φ0 output from Antic to the CPU, and it is a direct line from one to the other Then to add further confusion, in the XE series (including the XEGS) they also buffer the GTIA chip select line as well. In the XL series just like the XEGS they do not buffer the Φ0 signal, but then only in the 1200XL they do buffer the R/W line going to U22 pin-7 (2D) of a 74LS375 4-bit latch which appears to be for creating a latched read/write for DRAM. So bottom line... can I just get by with the 74AC08 PH2 buffer only (using the series resistor) and ignore all this other gobbly goop random buffering of other signals? And to be clear, this is in reference to my new 1088XEL project. It would be so cool if I could chat with the Atari engineers and pick their brains as to why some of these decisions were made . - Michael Edited January 23, 2017 by mytekcontrols Quote Link to comment Share on other sites More sharing options...
+tf_hh Posted January 24, 2017 Share Posted January 24, 2017 So next on the agenda, will be to scope out the Φ0 signal coming from Antic over to the CPU. In most of the Atari iterations, this signal is also buffered by another AND gate. Since the Φ0 signal is not distributed to anything else, I am curious as to why this was done. Part of me suspects that it has to do with the delayed buffered Φ2 signal, and perhaps this an attempt to bring the timing back into alignment. Any other theories? IMHO the reason why Atari did buffer the PHI0 signal is the poor transient quality of some ANTIC. Falling edge is mostly absolute fine, but rising edge... looks sometimes more than a sine wave - I assume that the LS08 buffer part is only used to get better transitions and signal quality. 1 Quote Link to comment Share on other sites More sharing options...
ijor Posted January 24, 2017 Share Posted January 24, 2017 Possibly PHI0 buffering was inherited from the 800/400 design that generated PHI2 externally. And at least in some cases, seems that a NOR or NAND gate was used just for the purpose of negating the signal and because it was available. Delaying PHI0 is significant because it alters the relation between FP0 and PHI2. It is very possible that this is relevant for some of the analog/heat dependent GTIA tricks. And too much delay and probably GTIA/CTIA will start having synchronization problems. Regarding series resistor and impedance matching. Shouldn't this be implemented at the other end? Precisely because it depends on what exactly you connect. Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 24, 2017 Author Share Posted January 24, 2017 IMHO the reason why Atari did buffer the PHI0 signal is the poor transient quality of some ANTIC. Falling edge is mostly absolute fine, but rising edge... looks sometimes more than a sine wave - I assume that the LS08 buffer part is only used to get better transitions and signal quality. Thanks for analysis I'll be scoping this today, and also try adding the Φ0 buffering with one of the spare 74AC08 gates and see what that looks like as well. Possibly PHI0 buffering was inherited from the 800/400 design that generated PHI2 externally. And at least in some cases, seems that a NOR or NAND gate was used just for the purpose of negating the signal and because it was available. Delaying PHI0 is significant because it alters the relation between FP0 and PHI2. It is very possible that this is relevant for some of the analog/heat dependent GTIA tricks. And too much delay and probably GTIA/CTIA will start having synchronization problems. Regarding series resistor and impedance matching. Shouldn't this be implemented at the other end? Precisely because it depends on what exactly you connect. Hi ijor If there is a signal integrity problem as tf_hh suggested, then I can certainly still see the need for the buffering on the Φ0 signal. And since the 74AC08 has shown the ability to cut propagation delays by 2/3 of the formerly used 'LS' part, introduced delays should not be an issue (hopefully). My understanding is when terminating transmission lines, is that both a series and parallel (to GND) is often used, with the parallel always being on the end of the line, and a series resistor directly following the driver (i.e., 74AC08 buffer). Sometimes the parallel termination will actually be a voltage divider with one resistor to VCC and the other to VSS. Here's a pretty cool simulation of what happens: LINK - Michael 1 Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 24, 2017 Author Share Posted January 24, 2017 (edited) Phase 0 (un-buffered)... Phase 0 (Buffered)... I'll have to add in a series resistor to clean up the 74AC08 over/undershoots as what I saw with Phase 2. Resistor added... - Michael Edited January 24, 2017 by mytekcontrols 2 Quote Link to comment Share on other sites More sharing options...
ivop Posted January 24, 2017 Share Posted January 24, 2017 Perhaps you can try one of these to clean up the clock signals? http://www.nxp.com/documents/data_sheet/74HC7014.pdf 1 Quote Link to comment Share on other sites More sharing options...
+mytek Posted January 24, 2017 Author Share Posted January 24, 2017 (edited) Perhaps you can try one of these to clean up the clock signals? http://www.nxp.com/documents/data_sheet/74HC7014.pdf Propagation delays with this device would not be good (looks much worse than the original 74LS08 device). The Schmitt-trigger action is likely the cause for this slow response time. Also if this were a fast switching device, we would still see the over/undershoot on the output. I also have a need for one true AND gate (dual trigger inputs to toggle the Light Pen input on ANTIC). So using the 74AC08 gives me the gates I need, and the fast switching desired for PH0 and PH2. Having to also use a resistor in series to clean up the over/undershoot for those particular signals is a very acceptable compromise - Michael Edited January 24, 2017 by mytekcontrols Quote Link to comment Share on other sites More sharing options...
ijor Posted January 24, 2017 Share Posted January 24, 2017 If there is a signal integrity problem as tf_hh suggested, then I can certainly still see the need for the buffering on the Φ0 signal. Yes, of course. But we are also wondering why Atari sometimes buffered the signal and sometimes not. If it was done because the quality of the signal, it should probably be implemented always. Unless the problem is with the older Antic revision and was fixed in the newer Antic rev? Btw, the rising edge of that wave is rather slow. Just checked both the schematics and the datasheet, and it is not open drain. But possibly it has a driving power too small. Will take a look at the layout later. Quote Link to comment Share on other sites More sharing options...
+tf_hh Posted January 25, 2017 Share Posted January 25, 2017 Yes, of course. But we are also wondering why Atari sometimes buffered the signal and sometimes not. If it was done because the quality of the signal, it should probably be implemented always. Unless the problem is with the older Antic revision and was fixed in the newer Antic rev? Hmm, I think this will be contradictory to the ANTIC mods done on most XE mainboards. On all XE mainboards I´ve seen only the newer ANTIC "E" series are used with datecodes of 1983 or later. IMHO all these patches and odd additional circuits done by Atari factory are needed only due to the fact, that Atari mostly purchased the sediments of DRAM production charges - 20 years ago, when I (and most others too, I think) built memory expansions using DRAMs instead of SRAMs, a lot of timing issues and problems were normal. In germany, Klaus Peter´s "mega-RAM" was a horrible one, making a lot of trouble - not only the refresh issue. In most cases, changing all existing eight 4164 main memory DRAMs to a good, tested series, all matching from one lot, fixes the problem. More than patching PHI2 and so on... Because every timing issue around ANTIC ends up in graphical issues (sparks, wrong colors, wrong pixel, moving chars and so on), Atari mostly did these patching to make their cheap, sometimes heavy mixed DRAM garbage work. My 2 cents 2 Quote Link to comment Share on other sites More sharing options...
Level42 Posted August 30, 2017 Share Posted August 30, 2017 I love reading this stuff 3 Quote Link to comment Share on other sites More sharing options...
+mytek Posted August 30, 2017 Author Share Posted August 30, 2017 I love reading this stuff In the end it came down to using a 74F08 when developing the 1088XEL, which took the last bit of flakeyness out of the system, and it would likely work just as well in a real A8 system. - Michael 4 Quote Link to comment Share on other sites More sharing options...
_The Doctor__ Posted November 11, 2017 Share Posted November 11, 2017 (edited) It will, the original 800 had to deal with many and varied cards being inserted into it as well as memory configs on the bus, the additional circuitry helped with that... remember also the pin that needed re wiring on the cartridge port to make new devices and carts work, that was swapped for timing as well. some old carts didn't work with that being changed but the gains outweigh the losses so the mod should be don on all 800's or a toggle switch to go between the two for purists... Edited November 11, 2017 by _The Doctor__ Quote Link to comment Share on other sites More sharing options...
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