Milestone Acheived!!! PCB Layout Completed
Updated Schematic and PCB Design View Document:
Believe it or not, I was able to use 12 mil traces and inter-track spacing on about 99% of the layout, only needing to drop down to 8 mil traces for a few of the tighter spots. For me this board marks an achievement in my life, being the most complicated PCB that I ever laid out, and likely will hold that record for the rest of my life
Yesterday I was showing Bob Woolley where this project was at, and he asked me if I was going to make an announcement when I had completed the board routing (at the time I was only 1 trace route away from completion). I said probably not until I had a completed 'working' board in my hands. Obviously I rethunk that. What made me change my mind was that this project has been disclosed bit by bit through out this topic, sharing my journey in the process. I thought... why stop doing that? If it fails to work when I get my first boards, that too is a part of this journey, and you'll see me grumble and then sit back down and fix whatever is wrong
There have been some minor changes. For one thing I had the logic backwards on the power control circuit related specifically to what state the gate of the P-Channel MosFet (Q1) needs to see to turn on. That happens to be GROUND and not +5 as I originally presumed. So luckily I was able to correct this oversight by doing a slight reconfiguration of the existing circuit where I had already provided an NPN transistor to optionally switch on an ATX style PSU (LOW = ON). Now I share that inverted output. The other change worth noting is that what I was calling my EUI (Enhanced Upgrade Interface), now has a new name and a new pin assignment. Basically I can thank Bob for giving me the idea of also including the /$D1xx select signal, so that in essence this thing really is a mini version of something akin to the PBI. So now I call it MPBI (Mini Parallel Bus Interface). Basically it provides an abbreviated version of a full PBI, and also provides some additional page select bits and a few other goodies as well. Its interface connector is a 30 position 0.1" pitch double row header, which is easily connected to via a ribbon cable. In its new form, it provides signals for both the Rapidus and VBXE, and makes for a simple parallel port as well. For full parallel bus applications, I have retained the original ECI card edge connection.
There might have been a few other changes, but it all becomes a blur after putting in hours and hours of layout time. Download the attached PDF file to see where the 1088 XEL is presently at. It also includes the board front and back images as above, but you'll be able to zoom in for a much finer detail.
After taking a few more days to verify that everything is good from a design rules standpoint, I'll be ordering 10 boards. Some of these will make there way into the hands of a few beta testers I've used in the past on some of my other projects, and the rest will be for me to stare at in wonder as I think "Where the heck did I find the time and the drive to take on such a project!" And of course I'll put a few to actual use, creating a couple of cased Mini-ITX systems to play with (and eventually demo at a future Atari gathering).
So yet another MIni-ITX Atari motherboard will soon take its place in history
Edit: I did remember a few of the other changes: Had to correct orientation of pin 1 on several connectors (Joy Sticks, MPBI, and RGB-Thru), also added left channel audio to pin 1 of RGB-THRU which automatically superimposes this signal onto the Sophia D-Sub 9 RGB connector by simply crimping a 10 pin IDC female 1" from where the ribbon cable leaves the Sophia board. BTW, Sophia when connected to my board in this fashion, will still have the originally provided connector as well as being routed out to the DIN-13 jack on the 1088 XEL. So either interface jack can be used for Sophia's RGB output.
Edited by mytekcontrols, Mon Mar 20, 2017 2:07 PM.