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TAL by any other name is ...?

PLD QI glue

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#1 helocast OFFLINE  

helocast

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Posted Tue Mar 28, 2017 1:38 PM

I'm sure this "wanted project" falls into a small subset of users aka 1%-ers, but has anyone come up with a full set of equations to describe the "glue chip" of the TI-99/QI motherboards?

Of all the "still existing" de-solder-and-pop-in-a-socket drop-in chips, the CD40050 isn't one of them. A very 1975 era FPLA (actually more of a fused, simple AND-OR array) barely predates this and the GAL didn't arrive on the scene until Lattice in 1984!

I've been beating myself up with only partial success. I don't know VHDL and I'm not sure the complexity of the project requires something on the order of a CPLD/FPGA anyway ... perhaps a 22v10++ ;-]

 

What seems most likely to me is that TI just carved out a large piece of silicon and deposited all the inverters, NANDs, ORS, NORs, and discrete flip-flops/latches of the 4A schematic on it in groups with interconnects and called it a day. It's even hard working backwards from 4A schematics when some of the QI signals of the glue chip don't share the same name between 4A and QI schematics.

 

I envision, but am I wasting my time in a PLA, CD40050 pin-compatible, small board design with additional solder pads (access points) of key logic results so that all the console upgrades like those at Mainbyte/Thierry/et al can be applied to these consoles as well?

Thanks for any input!

Attached Files



#2 Ksarul ONLINE  

Ksarul

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Posted Tue Mar 28, 2017 3:08 PM

Look at the HOMBRE chip description on WHT. It may be filed under the 99/8 logic diagrams, but it was intended for the LPC version of the /4A. The schematic for it is a gate-level schematic, so that should help you a lot.


Edited by Ksarul, Tue Mar 28, 2017 3:09 PM.


#3 helocast OFFLINE  

helocast

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Posted Tue Mar 28, 2017 3:45 PM

Look at the HOMBRE chip description on WHT. It may be filed under the 99/8 logic diagrams, but it was intended for the LPC version of the /4A. The schematic for it is a gate-level schematic, so that should help you a lot.

 

Thank you! I certainly recognize most of those signals. Took me a while to locate http://ftp.whtech.co...ic Diagrams.pdf

Onward and upward.



#4 helocast OFFLINE  

helocast

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Posted Tue Apr 4, 2017 10:10 PM

Giving back for those who can use the information. 1/2 solution done (combinatorial logic) and I'm currently working sequential logic which is kicking my you know what. ;)  

 

Attachments:

- Redrawn schematic as 256-color bitmap, full size (any lower resolution makes it barely readable like original provided above)

- Minterms in .txt format, both Product of Sums and Sum of Products

- Truth table of inputs/outputs, in comma-separated-value format (zipped because upload doesn't like raw .csv files?)

- All work in full analyzer program data file, also zipped, which can be immediately used in the following program

 

Program used to capture minterms/schematic is Logic Friday 1 http://sontrak.com/downloads.html (sorry, but can't afford CPLD/FPGA design software, but it's where I'm headed)

Attached Files


Edited by helocast, Tue Apr 4, 2017 10:11 PM.





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