I'm sure this "wanted project" falls into a small subset of users aka 1%-ers, but has anyone come up with a full set of equations to describe the "glue chip" of the TI-99/QI motherboards?
Of all the "still existing" de-solder-and-pop-in-a-socket drop-in chips, the CD40050 isn't one of them. A very 1975 era FPLA (actually more of a fused, simple AND-OR array) barely predates this and the GAL didn't arrive on the scene until Lattice in 1984!
I've been beating myself up with only partial success. I don't know VHDL and I'm not sure the complexity of the project requires something on the order of a CPLD/FPGA anyway ... perhaps a 22v10++ ;-]
What seems most likely to me is that TI just carved out a large piece of silicon and deposited all the inverters, NANDs, ORS, NORs, and discrete flip-flops/latches of the 4A schematic on it in groups with interconnects and called it a day. It's even hard working backwards from 4A schematics when some of the QI signals of the glue chip don't share the same name between 4A and QI schematics.
I envision, but am I wasting my time in a PLA, CD40050 pin-compatible, small board design with additional solder pads (access points) of key logic results so that all the console upgrades like those at Mainbyte/Thierry/et al can be applied to these consoles as well?
Thanks for any input!