I've been working on my bus decoder logic, and trying to square my understanding of 6502 bus cycles with reality, and also wrap my head around the quirks of the Atari XL PBI in particular... I keep turning up a lot of voodoo relating to PHI2 timing in particular, and have seen more than one mention of using a 74HC123 one-shot to help correct for this. Indeed, I even see an HCT123 on my SIDE2 cart, so there's obviously something to this. It's amazing such a slow bus (by today's standards) can be so finicky.
I've explored using a PLL in the FPGA as an alternative approach to a one-shot but so far that's led me down a dead end. I think the idea was sound, and indeed the FPGA I'm using does have PLL capability via the ALTPLL IP core (see https://www.altera.c...g/ug_altpll.pdf).... I was thinking I could feed it the 1.79MHz (NTSC) clock from PHI2 and derive a phase-correlated, but multiplied and/or phase-corrected clock off it so that I tweak the PLL to alter my bus timing as needed... Or drive a counter off of a multiplied version of the clock to adjust my cycle timing arbitrarily using taps off the counter.
Unfortunately I have discovered that the ALTPLL core has a lower limit of 5MHz on the input clock. Anything lower and there's no guarantee that the PLL can lock on to the signal across all conditions, so they disallow it. Sure, I could tell the tools I have a 5MHz clock and only feed it 1.79MHz but there's a fair chance it won't work at all, and a greater chance it won't work across temperature and other corner case conditions in the FPGA. It would be bad design.
Anyway I'm still brainstorming... I have a 50MHz clock that is completely asynchronous to the PHI2 clock, and I think with some clever techniques I can do some similar cycle timing adjustments with it.... but as part of the brainstorming process I'm trying to collect info that's out there relating to 6502 bus timing and specifically the issues on the 8-bit Atari bus because of any quirks they may have introduced with cost-savings, etc.
I'll try to collect and post interesting links relating to 6502 and PBI bus timings in particular as I find them.. Here are some... Please share if you've got anything up your sleeve.
- A recent thread Starman started, a few folks chimed in on with some general PBI info and articles (includes 4-part Antic article that I made into a single PDF): http://atariage.com/...-port-docsinfo/
- This old post by Matthias Reichl in 2006: https://groups.googl...bit/JwWqzcyqQ3Y
- MEtalGuy66 rant: http://atariage.com/...ction-standard/
- This old AA thread with a few tidbits of good info: http://atariage.com/...ew-pbi-devices/
- Old Candle thread: http://atariage.com/...-info-required/
- This is a bit off topic and more about 65816 timing, but it has some good visual presentation: http://laughtonelect...CPU Timing.html
Edited by TangentAudio, Tue Apr 4, 2017 7:07 PM.