Github VHDL is only slightly out of date (mainly test changes from last night), but the reset logic is still not done because I've been lazy. I've been 'cheating' so far, since it gets reset after programming and power cycle.
Yes, but the issue is you have not defined, anywhere, what 'reset' means, even from power on/programming 'reset'. So it's entirely possible something is coming up asserted when it shouldn't be, or something else like that, and mapping in the ROM during boot time when it should probably be mapped out.
Unfortunately, it's hard for me to decipher VHDL having learned systemverilog in school, so I'm also not entirely sure your HDL is correct, although I'm not saying it isn't. I just can't tell.
One thing I notice is that you only seem to be updating data_dir on the rising edge of phi2. Ideally, this should be purely combinational based on the address, r/w line, and the *state* (not the edge) of phi2. Of course, doing so could violate hold times on the 6502....
Also, can I ask your experience/background with programmable logic, computer systems, etc.? It helps to have a reasonable understanding of where you're at in terms of what you do and don't know.
Edited by Joey Z, Thu Apr 13, 2017 10:15 AM.