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TIPI - TI-99/4A to Raspberry PI interface development


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#51 jedimatt42 OFFLINE  

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Posted Tue May 9, 2017 12:56 PM

"TIPI", I like what's happening here, looking forward to it. Will this work with a raspberry Pi 3, and could the code be ported to a beaglebone? Thinking out loud, don't know anything about them, but do have two Beaglebones, white and black. I am going to experiment in a few months and see if I can go in the same direction. Cool things going on in the TI community ;-)

 

We've used a PI 3 to date.  The PI side code is all python so far. Although I've started working on a C library for python to get some signalling performance back.  I want to reduce the number of wires to the PI's GPIO, but that means more GPIO operations, which turns out to get slow. Khz in python, instead of Mhz in C... 

 

-M@



#52 --- Ω --- OFFLINE  

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Posted Wed May 10, 2017 7:54 AM

Hi Corey, 

   Could you please label the three items in the photo.  Also, will this really ALL be in one package upon completion?

 

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#53 jedimatt42 OFFLINE  

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Posted Wed May 10, 2017 8:56 AM

Since that photo is from my hardware, I'll go... ( Did you get a closeup of Corey's wire wrap edition? )

A - a Raspberry Pi breadboard adapter. This is called a PI Cobbler.
B - a Mojo FPGA dev board, the big chip is a Spartan 6 LX9 (this will not be in the final version)
C - a Raspberry Pi 3

Will it fit? Sure. Except the Raspberry Pi.

The parts on the breadboard are gross overkill for this project. The FPGA is effectively 1000 logic chips, and a pile of RAM. I'm using it to prototype an eprom 2 latches, 2 shift register, a flip flop for a crubit, and the address decoding logic. That all gets expressed in verilog.

Other chips on my breadboard are logic level converters. 5v to 3.3v where needed.

A CPLD such as what is on the FinalGROM99 is more than capable of replacing all my chips and the FPGA, except it doesn't have RAM built in. So we'll use the CPLD, and an EPROM.

I'm working on reducing the pin count to the Raspberry Pi, so we can use a small package CPLD.

And then I want to include a 74'244/5 to act as a logic level converter heading back into the 4A's data bus.

So, 3 chips, some LEDs, a connector to attach to the 32k board, and a small ribbon connector out to the Raspberry Pi.

I do not intend to attach the PI 3 directly.. the PI 3 needs cables like USB power and optionally ethernet and it would be awkward to attach and use the USB power. So I want to keep that on a flexible ribbon cable.

The PI cobbler is 40 pins, but I only really need 8. (Based on theoretical design I wrote down last night)

-M@

#54 --- Ω --- OFFLINE  

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Posted Wed May 10, 2017 9:10 AM

I like the idea of a plug-in board to the side of your 32K card and the RPi being on a cable plugged into that.

I've never needed, owned or used a RPi before, but this project is so exciting and shows so much promise for the future that I have bite the hook!  



#55 jedimatt42 OFFLINE  

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Posted Sun May 21, 2017 1:19 PM

I've been working on a few internal things:

 

Updating schematic toward what a production board should be. I hate KiCad usability, I love KiCad's availability. 

 

C library module for python, to handle the GPIO directly.  This boosted my send rate to the TI from 4k/sec to 6k/sec.

 

I worked out a second CRU bit, so the DSR powerup routine is actually signalling the Raspberry PI with an interrupt to reset the PI side service scripts everytime the 4A console is back at the title screen.  This makes the python side robust... file handles are closed, sockets are closed, cached file contents are freed.  Great for a resilient experience.

 

And, I spent a ton of time watching MSX GR8NET videos yesterday, so I finally got off my behind, and implemented opcode 5 ( load program image ) for TIPI.HTTP special file handler. Here's a quick demo:

 

 

-M@



#56 Shift838 OFFLINE  

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Posted Sun May 21, 2017 9:23 PM

that is awesome!  loading programs from the web directly via TiPi....  Love it...



#57 Vorticon OFFLINE  

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Posted Mon May 22, 2017 5:56 AM

:thumbsup:  :thumbsup:  :thumbsup:

Are you going to put out some form of documentation for setup and use for the technically challenged?  :P



#58 --- Ω --- OFFLINE  

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Posted Mon May 22, 2017 9:13 AM

that is awesome!  loading programs from the web directly via TiPi....  Love it...

 

That's slicker than snot on ice!  The days requiring PC in the mix to get programs may soon be numbered.   :thumbsup:

I wonder if a 'new' version of something like DM2K will arrive on the scene shortly afterward that will allow a newbie to directory and download or simply run a program without having to know and type a long URL?



#59 --- Ω --- OFFLINE  

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Posted Mon May 22, 2017 9:14 AM

:thumbsup:  :thumbsup:  :thumbsup:

Are you going to put out some form of documentation for setup and use for the technically challenged?  :P

 

I'm hoping for pre-assembled & ready to install myself.  :)



#60 Sinphaltimus ONLINE  

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Posted Mon May 22, 2017 9:19 AM

So my 2017 wishlist is FG99 and TiPi.

Indeed an exciting year.

#61 --- Ω --- OFFLINE  

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Posted Mon May 22, 2017 9:24 AM

So my 2017 wishlist is FG99 and TiPi.

Indeed an exciting year.

 

Total agreement so far.  Of course I also want a WiFi UberGROM when/if they become available assembled for my second system.

My main concern at this point is continued software support for all the varied devices. 



#62 jedimatt42 OFFLINE  

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Posted Mon May 22, 2017 10:21 AM

:thumbsup:  :thumbsup:  :thumbsup:
Are you going to put out some form of documentation for setup and use for the technically challenged?  :P


The plan is to print and assemble boards for the technically challenged.

For the technically inclined, I'm trying to finalize using a parallel to serial input shift register, so my wiring to the Raspberry Pi is just 8 wires. After that, I'll update the github docs, and clean out the theoretical, in favor of the actual.

Mind, the Mojo FPGA dev board is not the target. The target is an Eprom, and a buffer chip, and an xc9572xl qf64 for all the glue.

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I need to find an 8 bit parallel input to 1 bit output shift register to model. I made something up in verilog, but my input clocking is goofy. I can tell I have fallen into one of those declarative vs. procedural traps with verilog. :(

-M@




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