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XEL-CF Compact Flash Adapter for 1088XEL (formerly XEL-I3)

IDE CF Incognito XEL

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#1 mytekcontrols OFFLINE  

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Posted Fri May 12, 2017 8:17 PM

I am attempting to create a simple IDE/CF interface for the 1088XEL's MPBI port (Mini-Parallel Bus Interface). The idea is to have it be supported by the U1MB BIOS in some fashion that is similar to the Side2 cart, but without all the bells and whistles this cart has (sans SDX and R-Time8). So to do this, it appears that loading the Incognito PBI BIOS into the U1MB might give us a simple software solution, since it only requires that the 8 basic IDE registers be accessed and mapped into the appropriate area (see FJC's comment below quoted from an earlier discussion Link Here)
 

Another option (easier for me, at least): use the Incognito decoding address:
 

IDE_DATA	equ $D1E0
IDE_ERR		equ $D1E1
IDE_SCNT	equ $D1E2
IDE_SNUM	equ $D1E3		; LBA 0
IDE_CYLL	equ $D1E4		; LBA 1
IDE_CYLH	equ $D1E5		; LBA 2
IDE_HEAD	equ $D1E6		; LBA 3 ($Ex)
IDE_STAT	equ $D1E7
Incognito has no alternate status register or hardware IDE reset - just the bare eight registers. Note that this would require a custom BIOS, of course (Incognito PBI BIOS flashed to U1MB).

 

 

 

So my plan is to modify the original MyIDE ][ internal interface circuit as shown in Mr Atari's site (reference), and do some extra decoding to make it point the IDE registers directly at $D1E0-7. Below you will see my first proposed design to hopefully accomplish this.

 

1gJexyR.png

 

Here's the complete MPBI port as it is implemented on the V1.1 XEL...

 

XFnFFf2.png

 

I plan to use one of these CF-to-IDE adapters while prototyping...

 

s-l500.jpg

 

Although the preliminary schematic doesn't show it, there will be a MPBI pass-thru provided as well.

 

- Michael

 



#2 Van OFFLINE  

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Posted Sat May 13, 2017 12:25 AM

Interesting.

You can save a chip by using a '138 to decode then a quad NAND for the two NOT and OR gates.

The 138:

A4 - A1

A5 - A2

A6 - A3

/$D1- /E1

A3 - /E2

A7 - E3

Output from /Y7 = /$D1E0-7

Yogi

EDIT: also you could use ACT instead of F logic, uses less power and only slightly slower.


Edited by Van, Sat May 13, 2017 1:12 AM.


#3 ProWizard OFFLINE  

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Posted Sat May 13, 2017 1:24 AM

Don't forget the timing issues in this design!! These are adressed with a latch ttl and a capacitor. Iirc it was a 74ls573.

#4 mytekcontrols OFFLINE  

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Posted Sat May 13, 2017 9:19 AM

Yes I now see the advantage, starting from scratch instead of piggybacking a current design pays off by allowing the one chip reduction (I'll revise the schematic and repost it by tomorrow). Thanks Yogi.

Prowizard thanks for the tip, I had forgotten about that Phi2 issue. Be interesting to see if that is still an issue in the XEL as well. I'll start out without the delay circuit to see what happens, but hold it in reserve if I encounter problems.

FJC uploaded a special untested version of the Incognito PBI BIOS in the previous topic that these discussions began in. If that does the trick in this project I'll post it in this topic as well.

Now I have to put together a Digi-Key parts order so that this journey can truly begin.

- Michael

#5 Van OFFLINE  

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Posted Sat May 13, 2017 9:41 AM

Had to look-up the '573 fix and thought I'd drop the link here http://atariage.com/...47#entry2544003



#6 gozar OFFLINE  

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Posted Sat May 13, 2017 10:27 AM

I am attempting to create a simple IDE/CF interface for the 1088XEL's MPBI port (Mini-Parallel Bus Interface). The idea is to have it be supported by the U1MB BIOS in some fashion that is similar to the Side2 cart, but without all the bells and whistles this cart has (sans SDX and R-Time8). So to do this, it appears that loading the Incognito PBI BIOS into the U1MB might give us a simple software solution, since it only requires that the 8 basic IDE registers be accessed and mapped into the appropriate area (see FJC's comment below quoted from an earlier discussion Link Here)
 

 

 

Would this be something current U1M installed machines could use to hang a CF card off of the PBI/ECI, therefore freeing up the cartridge port?



#7 Kyle22 OFFLINE  

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Posted Sat May 13, 2017 12:28 PM

This just keeps getting better and better!  This would also work nicely in a (modded w/ 800XL MMU & OS) 1200XL picking up most of the signals from one of the OS ROM sockets. $D1xx is on pin 14 of the MMU, and B02 and R/W are also easily found.

 

This would allow us with U1Ms to have our cart port back.



#8 mytekcontrols OFFLINE  

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Posted Sat May 13, 2017 4:37 PM

Gozar my primary target will be for the XEL's MPBI port, but there is no reason that this couldn't be made to work from a standard PBI (either XL or XE). This project really justifies the reason why I provided a special abbreviated version of the PBI in the XEL, and likely isn't the only device that will take advantage of it, although I have a feeling it is going to be the best (and most useful) device that will. After I get the XEL version working, I might entertain the idea of making a standard A8 compatible one.

Thank you for your interest.

As Kyle pointed out, this really is about getting the cart port freed up, and at the same time getting rid of redundant hardware that the U1MB already provides.

- Michael

#9 mytekcontrols OFFLINE  

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Posted Sat May 13, 2017 10:47 PM

Suggestions incorporated... now considered as Prototype 2 design.

 

2JAEQSN.png

 

Had to slightly modify 74F138 decoding to properly cover range of interest $D1E0-$D1E7. Retained '74F' series for decoding and read/write aspects, since this appeared to yield best compatibility across various CF cards (well within power envelope for recommended XEL 2 Amp power adapter).

 

- Michael



#10 Kyle22 OFFLINE  

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Posted Sat May 13, 2017 11:39 PM

How about a 16 bit version?

 

:)

 

Ugh, another Edit:

 

To clarify, by 16 bit, I mean only the interface. This has nothing to do with what CPU you have.


Edited by Kyle22, Sat May 13, 2017 11:41 PM.


#11 mytekcontrols OFFLINE  

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Posted Sun May 14, 2017 12:15 AM

How about a 16 bit version?

 

:)

 

Ugh, another Edit:

 

To clarify, by 16 bit, I mean only the interface. This has nothing to do with what CPU you have.

 

What is the advantage that would justify the added complexity? Unless I'm far off base, is this in reference to missing out on half the drive's capacity?

 

- Michael


Edited by mytekcontrols, Sun May 14, 2017 12:21 AM.


#12 Van OFFLINE  

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Posted Sun May 14, 2017 7:10 AM

Suggestions incorporated... now considered as Prototype 2 design.

 

2JAEQSN.png

 

Had to slightly modify 74F138 decoding to properly cover range of interest $D1E0-$D1E7. Retained '74F' series for decoding and read/write aspects, since this appeared to yield best compatibility across various CF cards (well within power envelope for recommended XEL 2 Amp power adapter).

 

- Michael

Looks good, sorry I was too hasty with my first post. I was too focused on avoiding an extra gate, but there is a spare NAND which works out nicely. The output should have been from /Y6 but even with that my configuration would have selected blocks of 16 addresses. Page $D1 is used a bit, so fully decoding only the 8 needed addresses is a must.

Yogi



#13 mytekcontrols OFFLINE  

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Posted Sun May 14, 2017 7:59 AM

Looks good, sorry I was too hasty with my first post. I was too focused on avoiding an extra gate, but there is a spare NAND which works out nicely. The output should have been from /Y6 but even with that my configuration would have selected blocks of 16 addresses. Page $D1 is used a bit, so fully decoding only the 8 needed addresses is a must.
Yogi


No need to apologize. You inspired me to go down a much better path that in the end still reduced the requirement by one gate. So I look at it from the angle that 'we' both contributed to this design as a team effort. Thank you for steering me in this direction.

- Michael

#14 Van OFFLINE  

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Posted Sun May 14, 2017 9:37 AM

All credit goes to you for sure, and no need to thank me, just glad I can help a little.  I'm just 'nerding out', playing with logic and the '138 is really a fun chip for addressing.

 

Analyzed  the designs yet again; even though my original decoder isn't clear (even to me; had to fill out a truth table), it does selects 8 blocks of 8 addresses but they are spaced 16 bytes apart: /Y0 = $80-$87, /Y1 = $90-$97 ... /Y6 = $E0-$E7, /Y7 = $F0-$F7. So yes it violates the KISS rule but does the job :)

So it's debatable to change your V2 design just to save the NAND, as the gate is a spare, but might help with routing and save a little with the prop delay.

 

Anyway really like your 'streamlined' myIDE, it'll make a nice addition to the 1088 XEL :) The M-PBI is one of my favorite features on the board, from a long list of great features.

Yogi



#15 Kyle22 OFFLINE  

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Posted Sun May 14, 2017 9:54 AM

 
What is the advantage that would justify the added complexity? Unless I'm far off base, is this in reference to missing out on half the drive's capacity?
 
- Michael


Yes, that's exactly what I was thinking.

#16 mytekcontrols OFFLINE  

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Posted Sun May 14, 2017 10:28 AM

All credit goes to you for sure, and no need to thank me, just glad I can help a little.  I'm just 'nerding out', playing with logic and the '138 is really a fun chip for addressing.

 

Analyzed  the designs yet again; even though my original decoder isn't clear (even to me; had to fill out a truth table), it does selects 8 blocks of 8 addresses but they are spaced 16 bytes apart: /Y0 = $80-$87, /Y1 = $90-$97 ... /Y6 = $E0-$E7, /Y7 = $F0-$F7. So yes it violates the KISS rule but does the job :)

So it's debatable to change your V2 design just to save the NAND, as the gate is a spare, but might help with routing and save a little with the prop delay.

 

Anyway really like your 'streamlined' myIDE, it'll make a nice addition to the 1088 XEL :) The M-PBI is one of my favorite features on the board, from a long list of great features.

Yogi

 

I missed the /Y6 possibility, but I knew that /Y7 as you had originally mentioned wasn't quite what I was after so that's what led me to rearranging things and tossing in the spare NAND gate as an inverter to give me a 3rd 'NOT' enable.

 

 

Yes, that's exactly what I was thinking.

 

This takes me back to the early days of Bob Woolley's SmartIDE proposal and the debate that went on soon after about only utilizing half the drive. Even back in that time period (90's?) this didn't seem like a biggie considering the size of typical IDE Hard Drives that were available as compared to how small most A8 files really were. Now days it seems to be even less of a concern, since A8 files haven't grown much in size, yet Hard Drives and CF cards are orders of magnitude larger than their earlier counterparts. The only exception I can think of would be for those that want to watch streaming movies on their A8, although I gotta say after the novelty wears off streaming on a modern machine makes a lot more sense (but it sure would have been super cool in the 90's). So long story short, I don't think I'll be implementing 16 bit access in this first design.

 

- Michael



#17 ivop OFFLINE  

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Posted Sun May 14, 2017 11:36 AM

With the introduction of CF cards, the old XT-era 8-bit mode came back in the (P)ATA standard. Most IDE harddrives didn't support it any longer as it became optional when 16-bit ISA was mainstream, but for CF cards it is mandatory. In this mode, the full 512-bytes can be read through an 8-bit register. I'm fairly sure the Atari FAT32 loaders use this mode, too.



#18 Kyle22 OFFLINE  

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Posted Sun May 14, 2017 5:17 PM

I have found that most Type-II MicroDrives don't work correctly (or at all) with the 8 bit interface.  Their data sheets say they will, but they don't.  The only one I found that works is a Seagate ST-1.

 

Why this is important is because the Type-II's are DIRT CHEAP. I can't say that loud enough. :)



#19 mytekcontrols OFFLINE  

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Posted Sun May 14, 2017 6:27 PM

I have found that most Type-II MicroDrives don't work correctly (or at all) with the 8 bit interface.  Their data sheets say they will, but they don't.  The only one I found that works is a Seagate ST-1.

 

Why this is important is because the Type-II's are DIRT CHEAP. I can't say that loud enough. :)

 

Be informative to find out if those Type-II MicroDrives work in 8-Bit mode on another non-Atari interface. Because if they do, it could be a timing problem.

 

- Michael



#20 _The Doctor__ OFFLINE  

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Posted Sun May 14, 2017 7:49 PM

sorry but wasting half the drive is also a waste of time to access the drive as well... also with all the other items we could keep on the Atari this space does get eaten up... I intend to get all of the stuff off the pc and onto the Atari... in an Atari usable format if possible... with the continued development of GUI and not to mention the new games and conversion. the sound demos and videos, rasta images books etc... it seems that having it all contained by the Atari to displayed or printed by the Atari would be the coolest... the whole running to the PC for Atari stuff gets annoying......



#21 mytekcontrols OFFLINE  

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Posted Sun May 14, 2017 8:17 PM

sorry but wasting half the drive is also a waste of time to access the drive as well... also with all the other items we could keep on the Atari this space does get eaten up... I intend to get all of the stuff off the pc and onto the Atari... in an Atari usable format if possible... with the continued development of GUI and not to mention the new games and conversion. the sound demos and videos, rasta images books etc... it seems that having it all contained by the Atari to displayed or printed by the Atari would be the coolest... the whole running to the PC for Atari stuff gets annoying......

 

In the application I'm shooting for I won't be wasting half the drive space since this really is aimed at utilizing CF cards via the U1MB BIOS (Incognito flavor), which I'm assuming supports the CF 8-Bit mode. If someone wants to use a 'real' IDE Hard Drive on the XEL they would be better off doing so with a CART/ECI Parallel Interface board, and although it would take more room, there are larger cases with drive bays that would likely work for this.

 

I'm just trying to provide a solution that implements a Flash Drive in the same manner as the SIDE2 minus the redundancy of the stuff already integrated into the U1MB. And that will easily fit inside a compact Mini-ITX case with the XEL motherboard, while not taking over or requiring the CART port. Although in a pinch it could be used for a standard IDE Hard Drive interface, assuming one doesn't mind that half the drive is inaccessible, but as I said that is not the focus of this project. Just trying to keep things simple here.

 

- Michael



#22 mytekcontrols OFFLINE  

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Posted Fri Jun 2, 2017 5:06 PM

Update

 

Starting to do the initial layout for the PCB. The unmarked socket shown in the image as simply 'J' will be a pin-for-pin copy of J1, with either one serving as a pass-thru depending upon the application.

 

Qpd0k3V.png

 

Once again this is strictly a through-hole project for ease of assembly by DIY types. So to make that a bit more feasible, a carrier board is to be utilized for the CF card connector which can not be gotten in a through-hole configuration. These are remarkably inexpensive from the place across the sea (LINK).

s-l500.jpg

 

And it'll accept two of these for easy panel mounting.

621.jpg

The height of the board if plugged directly into the XEL's MPBI connector (using a right-angle female connector for 'J'), will sit fractions of an inch below the top panel on the taller Realan Mini-ITX case. So the idea is to have a slot cut in that panel for insertion of the CF card. If a male box header is used instead of the right angle female connector, then a ribbon cable can be used to position the board wherever you wish.

 

- Michael


Edited by mytekcontrols, Fri Jun 2, 2017 5:09 PM.


#23 mytekcontrols OFFLINE  

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Posted Mon Jun 5, 2017 10:28 PM

Board layout has been completed and a prototype order placed with EasyEDA. They have a simple built-in Gerber Viewer that you can use to verify your design. Here's an example generated for the Top and Bottom Views. Although it failed to generate the copper ground plane and associated connections to it on the Top Layer. I inquired about this via the site's Live Chat feature, and got an almost instant response stating that so long as the information is present in the gerber file, that there would be no problems with producing the board correctly.

 

2cnBQpP.png 8aDqPjF.png

 

So as a verification, I also uploaded the gerbers to OSH Park and got this rendering (which is correct). And I always double check my gerbers in GerbV an off-line viewer app on my Linux box.

 

 My3nfR6.png LQt7xgB.png

 

And here's the updated schematic.

Tyd5YBk.png

 

This design got updated from a 40 pin IDE to the 44 Pin version used by Notebook IDE Drives and Compact Flash Cards. The difference between the two, is that the power is supplied on the same connector with the IDE44 version.

 

Should be able to test this in about 2 weeks or sooner.

 

- Michael



#24 Van OFFLINE  

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Posted Mon Jun 5, 2017 11:08 PM

This is looking good, will make a very compact unit.

 

Just went to the seller's site, looks like all units come with a bent pin, must be a value added service :-D

Yogi



#25 mytekcontrols OFFLINE  

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Posted Mon Jun 5, 2017 11:26 PM

This is looking good, will make a very compact unit.

 

Just went to the seller's site, looks like all units come with a bent pin, must be a value added service :-D

Yogi

 

So you noticed that as well  :grin:  I'm kinda disappointed though that mine came without the bent pin (might have to send it back  ;) ).

 

- Michael







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