Dunno, see what Krikzz has to say wrt the EDs:
My opinion is that level shifters are the way to go BUT a simple resistor and how his flash cart works would already limit the potential for issues anyway so much so I am not loosing any sleep over it.
The worst carts in the EDs series according to that article have to be from the old series: MasterED v1, TBED v1, MegaED v1
[v2s have level shifters either everywhere or just excluding the databus which during gameplay is only used in read mode which means it's the 3V3 flash/PSRAM chip putting data on the 5V databus and that is perfectly safe, during flashing/writing Krikzz revealed that he lets the FPGA drive the databus as a speedup technique so once more it should be all safe as the FPGA is a 3V3 component, not sure if this last part is true for all the carts old included]
The issue with that article is the usage of an explosion as opening image and some alarmist tones without actual bench measurements .... I contacted the author via FB and he stated that once he has some more time he will capture the address bus and data bus with a scope to see how bad it really gets ... and that is really what I would like to see (I'm expecting very short overvoltages spike around 1/10 to 1/20 of his estimates to be fair but that's just speculation on my part)
Let's not forget that the way the article tackle the issue is from the point of view of feeding a constant 5V to all pins of a 3V3 flash chips which is not what happens in reality, not even close.
I don't think anyone (Krikzz included) defends the old design per se, just lowering the tones wrt the alarmistic nature of what's been said.
Here I say it: even using a couple of diodes to lower the voltage rail (some of the cheap multi do that) is acceptable as long as those diodes can dissipate the extra power .... say you need to drop 1.4V and you find 2 diodes each of 0.7V drop, if the chip ends up consuming a constant 20mA, each diode needs to be able to dissipate 20mA * 0.7V = 14mW which is really nothing:
that there can dissipate 500mW and conduct 200mA .... so even those chinese knockoff carts that use series diodes to lower the power rail are not as bad as depicted wrt that aspect mind you they still need resistors on the address pins to limit current/drop voltage ... but the point stands, he was attacking the usage of the series diode itself ... it's not ideal for sure but it's not that evil either (at 10+mA also that diode I linked the spec for would drop 1V dissipating then 20mW so a series of 2 would be feeding the chip just 3V and that is well within specs).
To be clear wrt cheap chinese knockoff, the series diode on the power rail is NOT the issue there.
In short wrt EDs you are NOT putting a nuke into your beloved old clunker.
NOTE: we all are assuming that the only ESD protection is by the 2 input diodes, reading around it turns out that that was the most basic old design to protect the delicate CMOS metal gate and companies have stepped up their game quite a bit by using 2 or 3 levels of ESD protection .... which means the diodes are not the only protection at play most likely ... that was because as geometry shrunk damage caused by ESD still during fabrication process was impacting the yield. I don't know if the specific flash used by the EDs is "well-protected" or not as the datasheet says very little about it but I suspect it fares way better than we seem to think.