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Altirra 2.90 released

altirra emulation

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#201 baktra OFFLINE  

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Posted Fri Sep 8, 2017 3:09 AM

If it is not too much, I would like to ask for another type of turbo tape - "Turbo Enabled  (Interrupt sense)". By interrupt I mean the SIO PIN 13. I would believe it would be almost the same as (Proceed Sense).

This is for the RAMBIT TURBO TAPE popular in the UK.

 

And I would have one question. Are the two PIA interrupts (PROCEED and INTERRUPT) egde-triggered or level-triggered? From the 6520 datasheet I understand that the IRQ is triggered when there is logical 0 on the pin. Is that correct?



#202 flashjazzcat ONLINE  

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Posted Fri Sep 8, 2017 5:02 AM

Not sure if it would be a major headache, but being to check a "disable" box next to a device's entry in the device tree would be useful when testing different hardware setups. Currently, if I want to temporarily disable - say - SIDE2, I have to completely remove the device and then add it again afterwards. Something like Windows' own device manager, where one can disable a device without actually removing it.



#203 Mclaneinc ONLINE  

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Posted Fri Sep 8, 2017 5:43 AM

Yup agree, I think I asked about it before but can't remember if there was an answer, bit of a pain if you have multiple devices and have to remove them all. I'd presume once the boxes are ticked a hard reset would be invoked to remap the emulated machine..

 

A lot easier than, having to retick multiple boxes for some devices..

 

Mind you, I don't have a clue how easy it would be but its a sound request..



#204 phaeron OFFLINE  

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Posted Fri Sep 8, 2017 11:24 PM

If it is not too much, I would like to ask for another type of turbo tape - "Turbo Enabled  (Interrupt sense)". By interrupt I mean the SIO PIN 13. I would believe it would be almost the same as (Proceed Sense).
This is for the RAMBIT TURBO TAPE popular in the UK.

 
Yeah, that's easy. I guess I need to put in a polarity invert option. Do you have an example schematic of the tape hardware?
 

And I would have one question. Are the two PIA interrupts (PROCEED and INTERRUPT) egde-triggered or level-triggered? From the 6520 datasheet I understand that the IRQ is triggered when there is logical 0 on the pin. Is that correct?

 

The inputs are edge-triggered and the output /IRQ is always level-triggered. The PIA is always configured to wait for a positive or negative transition on CA1/CB1 and pulls /IRQ in response. /IRQ is then held down until the interrupts are cleared by reading PORTA or PORTB. So basically, once the PIA detects the edge it's looking for, it holds the IRQ line active until it gets the 6502's attention.

 

A shortcoming of this feature is that the PIA is unable to read the current state of CA1/CB1. This comes into play with the Atari SX212 Modem, which uses the SIO Interrupt line to indicate whether it is in low speed (300 baud) or high speed (1200 baud). During normal operation, the modem handler sets the PIA to watch for a change in this line, and whenever it detects a change it updates its state and then flips the edge detection mode to watch for the next edge. The problem is that when the handler first loads it doesn't know the current speed and thus which way to configure the edge detection. As a result, it has to blindly try both 300 baud and 1200 baud on the modem to determine the current speed.
 

Not sure if it would be a major headache, but being to check a "disable" box next to a device's entry in the device tree would be useful when testing different hardware setups. Currently, if I want to temporarily disable - say - SIDE2, I have to completely remove the device and then add it again afterwards. Something like Windows' own device manager, where one can disable a device without actually removing it.

 

I've thought about it. Profiles can save the whole tree for now.

 



#205 Mclaneinc ONLINE  

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Posted Sat Sep 9, 2017 5:08 AM

Avery, I know you are busy and don't know if you spotted this thread re a new updated VAPI change

 

http://atariage.com/...t/#entry3841727

 

Just in case..



#206 serj OFFLINE  

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Posted Sat Sep 9, 2017 5:18 AM

nice !.
I hope Avery will accept this modification in the main branch.



#207 flashjazzcat ONLINE  

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Posted Sat Sep 9, 2017 5:19 AM

I've thought about it. Profiles can save the whole tree for now.
 


Great... Never thought of that. Will use profiles. :)

#208 baktra OFFLINE  

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Posted Sat Sep 9, 2017 1:46 PM

Phaeron, thank you for the explanation.

 

I have no schematic of the Rambit Turbo Tape, but it works almost the same as the Command-enabled turbo systems already supported by Altirra - PWM, except the signal goes to the INTERRUPT SIO pin, when turbo is enabled.

 

1.Turbo is enabled when COMMAND signal is active (LOW)

2.Signal goes to the INTERRUPT SIO pin (instead of DATA IN)

3.The circuitry doesn't change polarity of the signal on the tape. Natural polarity appears to be LOW-HIGH - examination of the writing and reading routines indicates this polarity. When the writing routine begins writing a pulse, it has SKCTL bit 7 set to 1 (forced break).

 

The reading routine is the following (combines interrupts from PIA and POKEY):

;===============================================================================
; RAMBIT Turbo System Loader for monolithic binary files
; Modernized version by BAKTRA Software
;
; Changes:
; - Program name is displayed (max. 16 characters)
; - Loading process is indicated by dark and bright green stripes displayed
;   on screen
; - DMA is disabled
; - To fit to three cassette blocks, "Data in EOF block is used"
;
; Notes:
; This loader is a skeleton and cannot be used as it is
; An external program must update the following:
; - Buffer range (RB_BUFLO...)
; - Instruction that set run address (stored in RAMLO)
; - PROGNAME field (optional)
;
; Assembly
; - Assemble with XASM 
; - LDRTYPE 0 indicates boot file. LDRTYPE 1 indicates binary file
; - COLORSYSTEM 0 indicates two color system, color changed for each byte.
; - COLORSYSTEM 1 indicates shades of single color changed for each bit.
;===============================================================================

 ICL "equates_mono.asm"
;
; Code equates
;
L008B       EQU $008B

;
; Start of code
;

             ORG $0080

 IFT LDRTYPE==0
             OPT H-
 ELS
             OPT H+
             ORG $0080
 EIF

 IFT LDRTYPE==0          
;Boot header
             DTA $01              ;Boot flag
             DTA $02              ;2 blocks           
             DTA $80,$00          ;Load address
             DTA $86,$91          ;Initialization address 
            
;-------------------------------------------------------------------------------
; Move last portion of the loader code from cassette buffer
;-------------------------------------------------------------------------------
RELO_P2     ldx  #128               ;Move 128 bytes of the EOF block
RELO_P2_L   lda  [1024-1],X         ;from cassette buffer
            sta  [$80+256-1],X      ;to the intended place
            dex  
            bne  RELO_P2_L            
 EIF

;-------------------------------------------------------------------------------
; Real program start
;------------------------------------------------------------------------------- 
START       ldx #$E0             ; Set RAMLO to $22E0
            stx RAMLO            ; 
            lda #$22             ; 
            sta RAMLO+1          ; 
            bne MAIN             ; And then jump to the main routine
            
RB_BUFLO    DTA $00              ;Buffer pointer LO    ($0A00)
RB_BUFHI    DTA $0A              ;Buffer pointer HI
RB_BFENLO   DTA $82              ;Buffer end pointer LO ($2382)
RB_BFENHI   DTA $23              ;Buffer end pointer HI

;===============================================================================
; Interrupt handlers
;===============================================================================

;First one-shot handler
IHANDLER1   pha                    ; Preserve A
            sty LOMEM+1            ; Zero checksum
            sta STIMER             ; Set value for timer (countdown to zero)
            lda #<IHANDLER2        ; Set new IRQ vector
            sta VIMIRQ             ; 
            lda PORTB              ; Read port B
            
            lda #$01               ; Jump to end of interrupt handler 
            bne IHANDLEREND        ; 

;Normal handler            
IHANDLER2   pha                    ; Preserve A
            lda #$01               ; Check IRQ status (timer 1)
            bit IRQST              ; 
            beq IHANDLEREND        ; If zero, jump to end of interrupt handler
            sta STIMER             ; Set value for timer (countdown to zero)
            cpy L008B              ; Compare $8B with 0
            rol LOMEM              ; Insert another bit (0 or 1)
            sta L008B              ; Store to $8B
 IFT COLORSYSTEM==1            
            txa
            ora #176
            sta COLBK
 EIF                        
            dex                    ; Decrement X
            lda PORTB              ; Read PORTB
            pla                    ; Restore A
            rti                    ; Return from interrupt

;Common end            
IHANDLEREND sty IRQEN              ; Disable interrupts
            sty L008B              ; Clear $8B
            sta IRQEN              ; IRQ enabled is timer 1 
            pla                    ; Restore A
            rti                    ; Return from interrupt
;===============================================================================            
; Main routine
;===============================================================================            
MAIN        ldy #16                ; Display title
NAMELOOP    lda [PROGNAME-1],y
            sta (SAVMSC),y
            dey
            bne NAMELOOP
            
            sty RTCLOK+2
WAITLOOP    lda RTCLOK+2
            cmp #100
            bcc WAITLOOP
            
            sei                    ; Disable hardware IRQ
            ldy #$00                
            ldx #$01                
            lda VIMIRQ             ; Push Immediate IRQ vector to the stack
            pha                     
            lda VIMIRQ+1            
            pha                     
            
            lda #<IHANDLER1        ; Set new Immediate IRQ vector ($0094)
            sta VIMIRQ             ; 
            sty IRQEN              ; Disable all IRQs
            sty NMIEN              ; Disable all NMIs (DLI,VBI,RESET)
            sty DMACLT             ; Disable screen display (DMA)
            sty VIMIRQ+1           ; 
            
            ldx #$34               ;Cassette Motor ON
            stx PACTL
            inx                    ;Set X to $35
            stx PBCTL              ;Direction control,A Intr. enable. Command low.         
            
            lda PORTB              ; Read PORTB
            ldx #$12               ; Set frequency of channel 1
            stx AUDF1              ; 
            cli                    ; Enable IRQs
            
            lda #$5A               ; Check LOMEM for $5A
            sta COLBK              ; Color
            
SYNCHRO     cmp LOMEM              ; 
            bne SYNCHRO            ; If not equal, loop
            
            ldx #$08               ; Loop (X is bit counter)
BYTEREAD    cpx #$00               ; 
            bne BYTEREAD           ; Until bit counter is zero
            
            lda LOMEM              ; Check current byte
            ldx #$08               ; Set bit counter to 8
            sta (RB_BUFLO),Y       ; Store current byte to buffer
            eor LOMEM+1            ; Eor with checksum
            sta LOMEM+1            ; Store updated checksum
 IFT COLORSYSTEM==0
            and #1                 ; Odd?
            bne BYTECOLOR1         ; Yes, use primary color
            clc
            lda #0                 ; No, use secondary color
            bcc BYTECOLOR2         ; Skip over
BYTECOLOR1  lda #176               ; Primary color
BYTECOLOR2  sta COLBK              ; Change background
 EIF            
            inc RB_BUFLO           ; Increment buffer pointer at $90,$91
            bne CHKHIBUF           ; 
            inc RB_BUFHI           ; 
            
CHKHIBUF    lda RB_BUFHI           ; Check high buffer pointer
            cmp RB_BFENHI          ; Check for end of file (ptr at $92,93) 
            bne BYTEREAD           ; 
            lda RB_BUFLO           ; 
            cmp RB_BFENLO          ; 
            bne BYTEREAD           ; If not EOF, continue
            
WTERM       cpx #$00               ; Loop 
            bne WTERM              ; Until X=0
            
            sei                    ; Disable IRQs
            pla                    ; Restore original IRQ vector
            sta VIMIRQ+1           ; 
            pla                    ; 
            sta VIMIRQ             ; 
            sty AUDF1              ; No frequency
            sty IRQEN              ; Disable interrupts
            lda PORTB              ; Read PORTB
            lda POKMSK             ; Read original pokey mask
            sta IRQEN              ; Re-enable previously enabled interrupts
            
            lda #$40               ; Re-Enable VBI
            sta NMIEN              ; 
            lda #$3C               ; Set PORTA and PORTB 
            sta PACTL              ; Motor off
            sta PBCTL              ; 
            cli                    ; Enable IRQs
            lda LOMEM+1            ; Read checksum
            beq FILL1              ; If zero, run program
            jmp COLDSV             ; Otherwise error and cold start
            
FILL1       ldx #[$FF-$80]         ; Clear storage from $80 to $FF
FILL_LOOP1  sta [$80-$1],x         ; 
            dex                    ; 
CLREND      bne FILL_LOOP1         ; Loop until X=0
            
FILL_LOOP2  sta [$100],x           ; Clear storage from $100 to CLREND
            inx                    ; Increment X
            cpx #[CLREND-$100]     ; Done ?
            bne FILL_LOOP2         ; No, loop

RUNIT       sty COLDST             ; Reset cold start flag
            lda #1                 ; Indicate successful disk boot
            sta BOOT
            jmp (RAMLO)            ; Run program

;===============================================================================            
; Data area
;===============================================================================                        
PROGNAME   DTA d'RAMBIT..........'

 IFT LDRTYPE=1
            *= $02E0
            DTA a(START)
 EIF
         



#209 voy OFFLINE  

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Posted Sat Sep 9, 2017 1:55 PM

Avery, I know you are busy and don't know if you spotted this thread re a new updated VAPI change

 

http://atariage.com/...t/#entry3841727

 

 

It would be great if a8rawconv would support enhanced ATX format... :)



#210 ijor OFFLINE  

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Posted Sat Sep 9, 2017 2:41 PM

 

It would be great if a8rawconv would support enhanced ATX format... :)

 

I didn't release a a8rawconv patch intentionally. As I said in the other thread, it's just in case the final ATX enhanced format would change (although probably it won't). This is to avoid images with the "experimental" format to be floating online. Once we settle, which would probably be shortly, a way to produce ATX enhanced images would be released one way or the other.



#211 DrVenkman OFFLINE  

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Posted Sat Sep 9, 2017 3:34 PM

Just for giggles I set up my drives on Altirra as Happy drives, to play around in emulation rather than with real disks on my newly-upgraded Happy 1050 drive. Even with accurate sector timing selected, I get a failure of the Happy Diagnostic when testing the High-Speed Transfer and rom tests. I'm using some 1050 roms that were posted by someone in a prior Altirra release thread, so I can understand the rom test might fail, but I'm a bit surprised the high speed read test would fail. 



#212 phaeron OFFLINE  

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Posted Mon Sep 11, 2017 11:49 PM

Just for giggles I set up my drives on Altirra as Happy drives, to play around in emulation rather than with real disks on my newly-upgraded Happy 1050 drive. Even with accurate sector timing selected, I get a failure of the Happy Diagnostic when testing the High-Speed Transfer and rom tests. I'm using some 1050 roms that were posted by someone in a prior Altirra release thread, so I can understand the rom test might fail, but I'm a bit surprised the high speed read test would fail. 

 

I assume you mean Happy 1050, since if you were able to get a plain 1050's ROM to work it would not support either the Happy diagnostics or high-speed test.

 

The high-speed test should work. Accurate sector timing doesn't matter as this is purely a communication test, no disk mechanism usage. I'd suggest starting with a firmware image that passes the diagnostic test first to rule out any issues with ROM modifications.



#213 Mclaneinc ONLINE  

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Posted Tue Sep 12, 2017 3:45 AM

Here are two known fine roms for Happy 1050

Attached Files



#214 Mclaneinc ONLINE  

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Posted Wed Sep 13, 2017 10:56 AM

Hi Avery,

 

I had a bug report sent to me, I've had a play with the /Type command and it seems to work as normal but I didn't play too much, here's the report I got

 

 

Hi Paul,

i am busy updating the Atari800 gb for mark.

do you know the creator of Altirra emulator?.
i sent him an email, with a bug report.

Didn't get a reply (wasn't expecting one really), but the emu was updated without the fix. icon_sad.gif

can you pass on the info please...

the command-line is broken.

(/TYPE) has been broken since v2.70, it works in v2.60.

batch file

Code:
altirra /basic /type "run`c~"

if you boot a tape with SIOpach enabled, it can send a comma to the key buffer.
you can see the problem with Arrow Of Death - Part I.
and all other chanel 8 adventures in the series.

adds a comma to colour TV (y/n) screen.
Add_CLP( /nobasic /casautoboot /siopatch)

works fine with this (no comma)
Add_CLP( /nobasic /casautoboot /nosiopatch)

there are other bugs, but that's the main one we need fixing for gamebase.

 



#215 phaeron OFFLINE  

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Posted Wed Sep 13, 2017 10:53 PM

Yes, yes, I know, I got the email. People need to have patience.



#216 Mclaneinc ONLINE  

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Posted Thu Sep 14, 2017 4:28 AM

My apologies, it wasn't meant to annoy you...I know you are busy, if anything I wondered if you might have missed that email from him because of your workload..

 

Again, sorry, I'm the last person on here that wants to aggravate you..

 

Paul..



#217 slx OFFLINE  

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Posted Fri Sep 15, 2017 1:55 AM

Found the following "anomaly" in a disassembly in the debugger:

 

double disassembly.jpeg

 

I selected disassembly from $9D5F. The disassembler tries to make sense of the preceding code as well and interprets the 7F at $9D5E as (i assume) an illegal opcode. This results in the disassembly using $9D5F as both an operand for the instruction at $9D5E and an opcode operand in itself.

 

While I recall that it is indeed possible (if beyond my skills) to code "double use" code like that, it is potentially confusing as it shows instructions that would not execute. It would be useful to maybe mark "double code" like that somehow.

 

Thanks for your excellent work which I have come to value a lot more since I started dissecting Shamus.

 



#218 Mclaneinc ONLINE  

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Posted Fri Sep 15, 2017 4:09 AM

Odd to try and disassemble from an odd byte in as much as most code is 2 bytes long with exceptions for RTS and NOP's etc, just seems a weird way to start normally half way through potential code?

 

This is from my limited knowledge so am probably wrong...(excuse my maths...oops..)


Edited by Mclaneinc, Fri Sep 15, 2017 4:48 AM.


#219 phaeron OFFLINE  

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Posted Sat Sep 16, 2017 1:39 AM

This is a failure of the backwards disassembler -- the instruction stream is only uniquely defined when read forwards, and reading backwards it is not possible to accurately determine the correct instruction stream. The currently disassembly view tries to guess by just picking an anchor some bytes back, aligning that point to an instruction boundary, and forward disassembling. The effect you see here occurs when the disassembler realizes that it is going to hop over the current instruction, so it forces the IP at that point. Probably could be improved by constructing a trellis from candidate opcodes, but it's always going to be a heuristic, especially when illegal opcodes are enabled.

 

And that's not even nearly as bad as 65C816 native mode, where the M/X flags have to be guessed too....



#220 EddyFree OFFLINE  

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Posted Sat Sep 16, 2017 2:13 PM

I'm experiancing interesting behavior on the cheat menu. My system or a bug? I'm running Altirra 290 32-bit on Windows XP SP2. It also happens with version 271.

Here's a detailed description:

Go to the cheater.
Add two or three addresses to the "cheats" window using the single right arrow.
Now select the very first cheat then delete it.
It will relocate to the bottom of the list and delete another of the cheats instead.

Now clear the cheat list and add three more.
Then select the very bottom one, take note of it, and then delete it.
Find the same address from the search results window that you just deleted and re-add it with the right arrow.
It will duplicate itself and remove another of the chosen addresses.

My apologies if this has already been reported.
 



#221 snicklin OFFLINE  

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Posted Sat Sep 16, 2017 11:56 PM

Feature Request: (nice to have but not essential):

 

I like the idea of a colour counter, like you see in this YouTube video: 

 

I could see it slowing down emulation, but if it is toggleable, this shouldn't be a problem.



#222 laoo OFFLINE  

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Posted Tue Sep 19, 2017 1:51 AM

Hi Phaeron!

I've started some non-trivial 65c816 programming and I've stumbled on some problems:

  1. Source level debugging is not working for bank other than $00, i.e. when the program is assembled to an address above $010000 the source code is not loaded by Altirra. Additionally setting breakpoint from source code file does not work ( e.g. "bp `source.asm:10`").
  2. Executing code in bank other than bank $00 in emulation mode with standard interrupts enabled should crash as returning to that bank after interrupt is impossible (interrupt does not push bank number and RTI does not pulls it back).
  3. Changing CPU speed resets some registers. In particular direct page register is being reset to 0 after changing speed.

I'll report more if I find something.



#223 drac030 OFFLINE  

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Posted Tue Sep 19, 2017 9:18 AM

Executing code in bank other than bank $00 in emulation mode with standard interrupts enabled should crash as returning to that bank after interrupt is impossible (interrupt does not push bank number and RTI does not pulls it back).


Indeed, in the emulation mode Altirra seems to fetch the interrupt vectors from K:$FFFx which would be totally cool, but unfortunately the real CPU does not behave this way (interrupt vectors are fetched from $00:$FFFx). The following program:
 
	.ou emui.com

	.or $0600
p6	lda #$38
	sta $d01a
	jmp p6
?end
	.or $2000
start	clc
	xce
	rep #$30
	.aw
	.iw
	ldx #p6
	ldy #p6
	lda #p6?end-p6-1
	phb
	mvn 0 1
	plb
	sec
	xce
	.ab 
	.ib
	lda #$0f
	sta p6+1
	jml >p6+$010000

	.or $02e0
	.wo start
seems to work on real hardware (making the display border white), while on Altirra it crashes.

Attached Files

  • Attached File  emui.zip   426bytes   4 downloads

Edited by drac030, Tue Sep 19, 2017 9:53 AM.


#224 phaeron OFFLINE  

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Posted Tue Sep 19, 2017 11:32 PM

Time to flush some of the backlog:

http://www.virtualdu...-2.99-test9.zip

http://www.virtualdu...9-test9-src.zip

 

  • Fixes crash in history view in cases where history is empty.
  • History view dynamically updates again on history enable/disable.
  • Fixed /type keys getting dropped during boot.
  • Added SIO interrupt line based cassette turbo. Needs testing as I don't have a test case for it.
  • IDE+2: Added option to protect NVRAM against corruption in case of reset during clock read. By default, the emulator will now shadow user writes and back out the clock read when saving the NVRAM. This can be disabled if you actually want to emulate the NVRAM getting trashed.
  • IDE+2: Internal SDX has priority over external cart. Note that the external cart option is finicky; as far as I can tell, it doesn't work when SDX is enabled because the SDX boot code turns the external cart back on.
  • Help: Added some info for IDE+2. (I just noticed the character encoding error in the TOC. I'll fix that....)
  • Cheats: Fixed sorting issues in the active cheat list.
  • CPU: PBK is now reset to 0 when taking interrupts in emulation mode on an '816.

PCLink timestamp: I'll have to research this more as Windows is finicky when it comes to when timestamps are updated. Applying the timestamps won't be an issue as long as I can get them to stick.

 

816 source bindings: Yes, this is a known issue. Bigger problem is that the symbol infrastructure isn't bank friendly right now either -- the MADS listing parser probably needs to be extended.

816 D=0 on speed change: Should already have been fixed. Current versions only reset registers if the CPU mode changes.

Color counter: Respectfully, I'll decline. IMO this is mostly for novelty purposes and it's not difficult to get out of a paint program after copying the screen from the emulator.



#225 baktra OFFLINE  

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Posted Wed Sep 20, 2017 8:52 AM

I have tested the  "SIO interrupt line based cassette turbo" feature with a wave file attached (The wave file contains normal boot part followed by a file stored in the Rambit Turbo Tape system).

 

Polarity of the rectangular pulses in the file is HIGH-LOW and the file loads just fine. With reversed polarity (LOW-HIGH) it doesn't load.

 

I expected that one polarity of the pulses will work and one will not (that's the nature of the RTT).

 

I didn't expect that the HIGH-LOW polarity will work and the LOW-HIGH polarity will not. I expected exactly the opposite. It is very much possible that I still don't understand the PIA interrupts and/or the RTT loader code.

 

 

 

 

 

 

Attached Files


Edited by baktra, Wed Sep 20, 2017 8:56 AM.






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