HiassofT Posted October 1, 2017 Share Posted October 1, 2017 (edited) I've uploaded the new V1.10 versions of the Mega Speedy software and CPLD logic to my website: CPLD logic V1.10 Software V1.10 Changes since the last V1.00a release: logic, software: add support for IS Plate mode software: update Speedy ROMs to fix highspeed issues on NTSC systems software: update MyPicoDos to 4.06 final version To use the newly added IS Plate mode you first have to update the Xilinx CPLD logic - pinout of the JTAG connector pads is here: http://www.horus.com/~hias/megaspeedy/logic/jtag-connector-pinout.jpg- and then update the config and flasher ROM slots. If you can't (or don't want to) update the CPLD logic just update the flasher and Speedy ROM slots with the new ROM versions. The IS Plate mode in flasher and Mega Speedy boot menu will be non-functional but everything else will work fine. PS: Big thanks to Nir Dary for info about IS Plate, I didn't know about this upgrade before! so long, Hias Edited October 1, 2017 by HiassofT 10 Quote Link to comment Share on other sites More sharing options...
Bikerbob Posted October 1, 2017 Share Posted October 1, 2017 Thanks HiassofT, I thought I was having issues with AtariClassic's sio2pc and the megaspeedy drive, but after a month of sitting because I was so busy I could not get it to repeat the issue. I also find with sio equipment that the order in which things are powered on, or software on say the PC side is initiated makes a difference. So maybe that had something to do with it also. So both of these I can use the FLash menu and update the drive correct? James Quote Link to comment Share on other sites More sharing options...
HiassofT Posted October 1, 2017 Author Share Posted October 1, 2017 (edited) To update the CPLD logic you need to use a Xilinx JTAG cable and the Xilinx programmer software (iMPACT) - same setup and procedure as for updating U1MB, The!Cart and a few other projects. The Mega Speedy ROM slots can be updated using the flasher (either booted from the Mega Speedy flasher or megaspeedy slots or loaded from the ATR via DOS). so long, Hias Edited October 1, 2017 by HiassofT Quote Link to comment Share on other sites More sharing options...
Level42 Posted October 1, 2017 Share Posted October 1, 2017 About the Xilinx Jtag cable.....would this work: https://www.ebay.com/p/1pc-Mini-USB-Blaster-Cable-for-CPLD-FPGA-Nios-JTAG-High-speed-Programmer/808168544?iid=232312954050 and will it work with the software you mention ? Quote Link to comment Share on other sites More sharing options...
ijor Posted October 2, 2017 Share Posted October 2, 2017 About the Xilinx Jtag cable.....would this work: https://www.ebay.com/p/1pc-Mini-USB-Blaster-Cable-for-CPLD-FPGA-Nios-JTAG-High-speed-Programmer/808168544?iid=232312954050 That's for Altera/Intel devices, not for Xilinx. And even for Altera, price is too low and probably the quality is as low as the price. I'd avoid and invest a little bit more. Quote Link to comment Share on other sites More sharing options...
Bikerbob Posted October 2, 2017 Share Posted October 2, 2017 To update the CPLD logic you need to use a Xilinx JTAG cable and the Xilinx programmer software (iMPACT) - same setup and procedure as for updating U1MB, The!Cart and a few other projects. The Mega Speedy ROM slots can be updated using the flasher (either booted from the Mega Speedy flasher or megaspeedy slots or loaded from the ATR via DOS). so long, Hias I own the U1mb as well as the Incognito.. so I would like to get the JTAG cable and software.. can anyone point me to what I should buy? James Quote Link to comment Share on other sites More sharing options...
Level42 Posted October 2, 2017 Share Posted October 2, 2017 (edited) Indead James, this would be great info...and what is so special about a cable except for a number of wires or is there electronics involved in the cable. I did some googling of course but this stuff confuses me.....also the software. Xilinx download page has loads of programs....what would,we need and is it free ? Edited October 2, 2017 by Level42 Quote Link to comment Share on other sites More sharing options...
HiassofT Posted October 2, 2017 Author Share Posted October 2, 2017 (edited) Buy a Xilinx USB platform cable like eg this one: http://www.ebay.com/itm/172298723356 The programmer software for the PC, iMPACT, is included in the ISE 14.7 Lab Tools package (you don't need to download the full ISE design suite). The Xilinx site changes every now and then, currently you can get it from Support->Downloads, then select the "ISE" tab. As for updating the CPLD: Either solder a 90° (angled) 8-pin header to the Mega Speedy PCB (pointing inwards and also angled a bit upwards, like you see in the picture) or just hook up the 6 cables to an 8-pin header, place that in the JTAG connector vias on the PCB and push against the header from the right side so the pins make good contact with the pads during programming. After connecting the JTAG cable power up your 1050, start iMPACT and update the Xilinx XC95144XL CPLD with the MegaSpeedy.jed file (just search the forum here for Xilinx update instructions if you are unsure how to use iMPACT). Then power off the 1050, unplug the JTAG cables and you are done. so long, Hias Edited October 2, 2017 by HiassofT 3 Quote Link to comment Share on other sites More sharing options...
+tf_hh Posted October 2, 2017 Share Posted October 2, 2017 I've uploaded the new V1.10 versions of the Mega Speedy software and CPLD logic to my website: CPLD logic V1.10 If any user isn´t able to update the Xilinx CPLD but want to do this without buying the needed cables and install the huge software packages, I offer a free-of-charge update service - only shipping costs (both ways) must be paid. Reasonable for european users I think, but of couse I will do it for everyone. Just drop me a PN. Jurgen 5 Quote Link to comment Share on other sites More sharing options...
Level42 Posted October 2, 2017 Share Posted October 2, 2017 Would you happen to be at the ABBUC meeting end of October Jurgen ? Quote Link to comment Share on other sites More sharing options...
+tf_hh Posted October 3, 2017 Share Posted October 3, 2017 Would you happen to be at the ABBUC meeting end of October Jurgen ? I will try to organize that 1 Quote Link to comment Share on other sites More sharing options...
ijor Posted October 3, 2017 Share Posted October 3, 2017 As for updating the CPLD: Either solder a 90° (angled) 8-pin header to the Mega Speedy PCB (pointing inwards and also angled a bit upwards, like you see in the picture) or just hook up the 6 cables to an 8-pin header, place that in the JTAG connector vias on the PCB and push against the header from the right side so the pins make good contact with the pads during programming. I always wonder why many of these boards aren't shipped with the JTAG/programming header already populated. Those of us not skilled in the art of soldering would appreciate it Does it increase costs significantly? Btw, I never paid attention, but I see now that the CPU is a CMOS variant, which of course is needed for the Speedy. But be aware that this would create some minor incompatibilities with firmware for the other drives that used the original NMOS 6502. Believe it or not, there are a couple of cases that depend on the original NMOS undocumented instructions that are not present in the CMOS parts. Quote Link to comment Share on other sites More sharing options...
HiassofT Posted October 3, 2017 Author Share Posted October 3, 2017 I always wonder why many of these boards aren't shipped with the JTAG/programming header already populated. Those of us not skilled in the art of soldering would appreciate it Does it increase costs significantly?Not 100% sure why the JTAG header isn't populated on the MegaSpeedy. Quite often these things are left out because Joe Average shouldn't tinker with it - and people with the skills to use programming cables usually also have the skills to solder or hold some connector in place while programming. Btw, I never paid attention, but I see now that the CPU is a CMOS variant, which of course is needed for the Speedy. But be aware that this would create some minor incompatibilities with firmware for the other drives that used the original NMOS 6502. Believe it or not, there are a couple of cases that depend on the original NMOS undocumented instructions that are not present in the CMOS parts.I'm aware of this and also was quite concerned about it during development. But during our tests we didn't run into incompatibility issues so it looks like it's a rather minor (or maybe even theoretical) issue. If you know about software that uses undocumented opcodes in the 1050 please tell us about it. Maybe it can be adapted to run on a 65C02 as well. so long, Hias Quote Link to comment Share on other sites More sharing options...
ijor Posted October 3, 2017 Share Posted October 3, 2017 If you know about software that uses undocumented opcodes in the 1050 please tell us about it. Maybe it can be adapted to run on a 65C02 as well. I believe there are a couple of cases. IIRC they are both Archiver/Super Archiver titles. It is part of the protection, so probably there are already cracked versions that run on the 65C02. Just noting that the originals won't work. Quote Link to comment Share on other sites More sharing options...
marcokitt2000 Posted October 11, 2017 Share Posted October 11, 2017 (edited) Buy a Xilinx USB platform cable like eg this one: http://www.ebay.com/itm/172298723356 The programmer software for the PC, iMPACT, is included in the ISE 14.7 Lab Tools package (you don't need to download the full ISE design suite). The Xilinx site changes every now and then, currently you can get it from Support->Downloads, then select the "ISE" tab. As for updating the CPLD: Either solder a 90° (angled) 8-pin header to the Mega Speedy PCB (pointing inwards and also angled a bit upwards, like you see in the picture) or just hook up the 6 cables to an 8-pin header, place that in the JTAG connector vias on the PCB and push against the header from the right side so the pins make good contact with the pads during programming. After connecting the JTAG cable power up your 1050, start iMPACT and update the Xilinx XC95144XL CPLD with the MegaSpeedy.jed file (just search the forum here for Xilinx update instructions if you are unsure how to use iMPACT). Then power off the 1050, unplug the JTAG cables and you are done. so long, Hias Hello HiassofT, I have buyed the flasher on 10/2 and today arraved. Wich cable do you use 7 pins or de 6 pins cable? Correction the 6 pins can you show some foto's Gr. Marco Edited October 11, 2017 by marcokitt2000 Quote Link to comment Share on other sites More sharing options...
HiassofT Posted October 11, 2017 Author Share Posted October 11, 2017 Use the cable with 7 single wires that came with the the Xilinx programmer. Connect them to the JTAG header as shown in this picture - except the cable labeled "INIT", leave this unconnected. VREF connects to VCC/3V3 BTW http://www.horus.com/~hias/megaspeedy/logic/jtag-connector-pinout.jpg so long, Hias 1 Quote Link to comment Share on other sites More sharing options...
marcokitt2000 Posted October 11, 2017 Share Posted October 11, 2017 Use the cable with 7 single wires that came with the the Xilinx programmer. Connect them to the JTAG header as shown in this picture - except the cable labeled "INIT", leave this unconnected. VREF connects to VCC/3V3 BTW http://www.horus.com/~hias/megaspeedy/logic/jtag-connector-pinout.jpg so long, Hias Hello HiassofT, Thanks it works great now pfff finally i can test little by little. gr. Marco Quote Link to comment Share on other sites More sharing options...
marcokitt2000 Posted October 11, 2017 Share Posted October 11, 2017 Hello HiassofT, Thanks it works great now pfff finally i can test little by little. gr. Marco Hello, Where can i download the is plate roms? And where are special info about the is plate. Gr. Marco Quote Link to comment Share on other sites More sharing options...
HiassofT Posted October 11, 2017 Author Share Posted October 11, 2017 Not sure if a dump of the IS Plate ROM is available somwehere on the 'net. Some more info about this upgrade is available here: http://atariage.com/forums/topic/254539-the-uk-1050-is-plate-upgrade/ http://www.page6.org/archive/issue_27/page_50.htm so long, Hias 2 Quote Link to comment Share on other sites More sharing options...
marcokitt2000 Posted October 12, 2017 Share Posted October 12, 2017 Not sure if a dump of the IS Plate ROM is available somwehere on the 'net. Some more info about this upgrade is available here: http://atariage.com/forums/topic/254539-the-uk-1050-is-plate-upgrade/ http://www.page6.org/archive/issue_27/page_50.htm so long, Hias Thnxxx Quote Link to comment Share on other sites More sharing options...
marcokitt2000 Posted October 22, 2017 Share Posted October 22, 2017 (edited) Buy a Xilinx USB platform cable like eg this one: http://www.ebay.com/itm/172298723356 The programmer software for the PC, iMPACT, is included in the ISE 14.7 Lab Tools package (you don't need to download the full ISE design suite). The Xilinx site changes every now and then, currently you can get it from Support->Downloads, then select the "ISE" tab. As for updating the CPLD: Either solder a 90° (angled) 8-pin header to the Mega Speedy PCB (pointing inwards and also angled a bit upwards, like you see in the picture) or just hook up the 6 cables to an 8-pin header, place that in the JTAG connector vias on the PCB and push against the header from the right side so the pins make good contact with the pads during programming. After connecting the JTAG cable power up your 1050, start iMPACT and update the Xilinx XC95144XL CPLD with the MegaSpeedy.jed file (just search the forum here for Xilinx update instructions if you are unsure how to use iMPACT). Then power off the 1050, unplug the JTAG cables and you are done. so long, Hias Hello HiassofT, I have one question anout the jtag xilinx programmer can we use it for other chips than xilinx? I have update both 1050 and i loved it an i hope the is plate rom will come soon i like to test it. Keep the good work. Greetings Marco Edited October 22, 2017 by marcokitt2000 Quote Link to comment Share on other sites More sharing options...
HiassofT Posted October 23, 2017 Author Share Posted October 23, 2017 I have one question anout the jtag xilinx programmer can we use it for other chips than xilinx?No, the programmer can only be used with the Xilinx Software (and Xilinx chips). so long, Hias Quote Link to comment Share on other sites More sharing options...
_The Doctor__ Posted October 26, 2017 Share Posted October 26, 2017 (edited) I've uploaded the new V1.10 versions of the Mega Speedy software and CPLD logic to my website: CPLD logic V1.10 Software V1.10 Changes since the last V1.00a release: logic, software: add support for IS Plate mode software: update Speedy ROMs to fix highspeed issues on NTSC systems software: update MyPicoDos to 4.06 final version To use the newly added IS Plate mode you first have to update the Xilinx CPLD logic - pinout of the JTAG connector pads is here: http://www.horus.com/~hias/megaspeedy/logic/jtag-connector-pinout.jpg- and then update the config and flasher ROM slots. If you can't (or don't want to) update the CPLD logic just update the flasher and Speedy ROM slots with the new ROM versions. The IS Plate mode in flasher and Mega Speedy boot menu will be non-functional but everything else will work fine. PS: Big thanks to Nir Dary for info about IS Plate, I didn't know about this upgrade before! so long, Hias Hias, can you in detail describe what the fix in the high speed code was for NTSC and what the difference was PAL v NTSC etc. Delving into SIO issues, this could make the scope of understanding much better Edited October 26, 2017 by _The Doctor__ Quote Link to comment Share on other sites More sharing options...
marcokitt2000 Posted October 27, 2017 Share Posted October 27, 2017 No, the programmer can only be used with the Xilinx Software (and Xilinx chips). so long, Hias Thnxx for the info.... Quote Link to comment Share on other sites More sharing options...
_The Doctor__ Posted October 27, 2017 Share Posted October 27, 2017 oh well programmer on the way, I was really looking forward to the how and the why step by step of the fix...what was wrong how the code worked and then how it was fixed why the differences did what they did and mattered... unless it's just let's cut the speed back who cares anyway type of fix then I'd be sad... Quote Link to comment Share on other sites More sharing options...
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