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how many CPU cycles in a scanline?


sanny

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Hi,

 

I've got two questions, which might be related.

 

The Altirra manual in section 2.3 states that there are 114 CPU cycles per scan line.

I've written a test program which disables Antic, DMA, and everything. Then it changes the background color register while the screen is displayed.

This test program needs to consume 105 cycles per scan line, otherwise the display gets distorted.

 

This is my first question. Is the Altirra manual wrong, or where do I lose the 9 (114-105) cycles?

 

For the second question look at the attached screen shot.

I expected the vertical bars to be evenly spaced.

I'm doing this in the program

; this should give evenly spaced horizontal bars
; but somehow that's not the case !??
        CYCLES  33
        STX     COLBK   ; 4 cycles (37)
        STA     COLBK   ; 4 cycles (41)
        STX     COLBK   ; 4 cycles (45)
        STA     COLBK   ; 4 cycles (49)
        STX     COLBK   ; 4 cycles (53)
        STA     COLBK   ; 4 cycles (57)
        STX     COLBK   ; 4 cycles (61)
        STA     COLBK   ; 4 cycles (65)
        STX     COLBK   ; 4 cycles (69)
        STA     COLBK   ; 4 cycles (73)
        STX     COLBK   ; 4 cycles (77)
        STA     COLBK   ; 4 cycles (81)
        STX     COLBK   ; 4 cycles (85)
        STA     COLBK   ; 4 cycles (89)
        STX     COLBK   ; 4 cycles (93)
        STA     COLBK   ; 4 cycles (97)
        STX     COLBK   ; 4 cycles (101)
        STA     COLBK   ; 4 cycles (105) -> 105 cycles total

This is for one display line. The code is repeated a few times to get "bars".

On the right half of the screen this looks like expected. But on the left half, the bars are thicker and the space between them is also larger. Can someone explain this effect to me? Maybe my missing cycles are somehow consumed by these bigger bars and spaces btw. them.

 

Attached are a precompiled exe and the (cc65) source code.

 

regards,

chris

post-18336-0-04410500-1510231058.png

test.xex

cycletest.zip

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I second what flashjazzcat said. You can see all refresh and DMA cycles in Altirra by pressing Shift-F8. If you do that when DMA is completely disabled you see the following pattern:

 

post-21021-0-19114400-1510246718.png

 

Notice that the positions of the DRAM refresh cycles correspond to the area where your bars are distorted.

 

Maybe you could even out the bars by intermixing ST* ABS, ST* ABS,Y and STA (ZP),Y instructions to adjust the width by one or two cycles at opportune moments since those take 4, 5 and 6 cycles respectively. You could also get 7 cycles if you force a page boundary to be crossed.

Edited by Xuel
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I think he wants to get as much out of each line as possible and wants to know how to get it all. so what is the answer 105 yes? and we are losing 9 instead of 8? why is there a difference pal/ntsc? covering the bases here...

Edited by _The Doctor__
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There's no difference in the number of cycles per line between PAL and NTSC. When DMA is disabled, DRAM refresh always consumes 9 cycles. The only time refresh takes fewer cycles is on "badlines" where some of the refresh cycles are blocked by character set index lookups depending on the width of the screen and the HSCROL status. See the timing diagrams in the Altirra Hardware Reference Manual for precise timings.

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I think he wants to get as much out of each line as possible and wants to know how to get it all.

 

Yes, that was the reason for my question.

 

Thanks for you answers.

 

Now I know there's nothing wrong with my program and that there are only 105 cycles available per scan line.

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Not a lot of point really, you'd end up with an incompatible system.

 

I suppose in doing it you'd get a "poor man's accelerated" machine with a blistering 9% or so performance increase.

The logic involved would simply be taking /REF and /HALT from Antic. Whenever /REF is active, override /HALT to bring it high as seen by the CPU.

But the problem is you'd also need to isolate the address bus since Antic is outputting a row address for the refresh.

 

So the poor man's accelerator ends up being more complex/costly than a rich man's one.

Edited by Rybags
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