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Strong-ARM DEMO

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#26 JeremiahK OFFLINE  

JeremiahK

    Chopper Commander

  • 210 posts
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Posted Sat Dec 23, 2017 12:30 PM

That sample sounds amazing, by the way.  Is it writing to the audio registers every scanline, at about 15000Hz?


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#27 ZackAttack OFFLINE  

ZackAttack

    Dragonstomper

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  • 747 posts
  • Location:Orlando, FL US

Posted Sat Dec 23, 2017 9:44 PM

That sample sounds amazing, by the way.  Is it writing to the audio registers every scanline, at about 15000Hz?

 

Yes, AUDC0 and AUDC1 are set to 0 during initialization and then AUDV1 and AUDV0 are written to every scan line. Fortunately the address of the AUDVx registers are just before the GRPx registers. So the JSR trick can be used twice in a row to update 4 registers before restoring the SP back to GRP1. This demo is only using 4bit samples though. $00 is always written to AUDV1, but that's only because I originally planned on doing 4bit and only asked for 4bit samples.



#28 iesposta OFFLINE  

iesposta

    River Patroller

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Posted Thu Dec 28, 2017 4:40 AM

...
$00 is always written to AUDV1, but that's only because I originally planned on doing 4bit and only asked for 4bit samples.


What bit would it be if you wrote to both AUDV0 and AUDV1?

I still suggest when trying to do a video image, use the start and end half scan line for an interlaced kernel and the doubled vertical resolution will not flicker.

#29 DirtyHairy OFFLINE  

DirtyHairy

    Moonsweeper

  • 471 posts
  • Location:Germany

Posted Thu Dec 28, 2017 4:45 AM

What bit would it be if you wrote to both AUDV0 and AUDV1?

I still suggest when trying to do a video image, use the start and end half scan line for an interlaced kernel and the doubled vertical resolution will not flicker.

 

 

Check out the other thread here for a discussion of this issue:  http://atariage.com/forums/topic/272948-large-audio-clips/ :)







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