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Erik's Tiny PEB


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#1 speccery OFFLINE  

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Posted Wed Jan 10, 2018 4:20 PM

I don't know if this is something that the world needs, or if it is even going to work, but I just finished the schematics and PCB design for my own take on the "mini/nano/whatever/quark" version of PEB. Since it's my version, I decided to call it simply Erik's Tiny PEB, as this is supposed to be small(ish).

 

I attach the schematics and current PCB layout. The schematics and the board are a bit of a mess, since the design is based on my existing and working "SD processor board", I just added a few things. I didn't want to layout everything again, so at places the board is dense and I haven't cleaned up the schematics.

 

Since the design is partially based on my existing work, theoretically this should work. The additions are:

  • 512K SRAM
  • 4MB SPI FLASH
  • TI-99/4A side port connector (created an Eagle symbol for it, hopefully that went ok)

Once I've verified the PCB and schematic design I'm going to send this off to China for PCB production. This should enable me to build a working prototype (hopefully).

 

The board is supposed to enable the following once it works (the way I imagine it - there are programmable components here and I don't know how much stuff will fit in, and it is hard to test without a prototype):

  • SD card storage support, with support for FAT, FAT32, SD and SDHC cards
  • 256K of paged RAM memory (and of course the standard 32K as a subset). I'm not sure if the standard paging will fit into the CPLD, but I think it will as I am not planning to store the page entries on the CPLD, but actually on external SRAM.
  • 256K of additional RAM which needs to provide support for DSR routines, potentially also for ROM cartridges and maybe even GROM.
  • ARM coprocessor for SD card support and other stuff. The CPLD is supposed to provide a simple transparent DMA engine, allowing the ARM to inject stuff from SD card to the TI-99/4A's memory expansion, on the fly. I have something like this working on my FPGA system, although that is a much more complex setup than can be done with these parts.
  • USB device interface (virtual serial port, running at 12 Mbps or something like that - this piece already works)
  • Serial port (3.3V level)
  • I2C port

 

The design is a weird derivative of my current FPGA system. I have connected my previous SD processor board to my FPGA TI-99/4A clone and it already allows me to load ROMs and GROMs from SD cards, my plan is to take that to the point that it would support TI's file system via a DSR. I have already a fair amount of firmware and other bits scattered in my various TI-related projects, so this is one attempt to hopefully gather some of those into a meaningful setup.

 

That, and the fact that I don't have a 32K memory expansion for my real TI-99/4A, so I wanted to get one and this seems to be what came out...

 

Erik

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#2 ti99iuc ONLINE  

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Posted Wed Jan 10, 2018 4:22 PM

Oh Coool !! In my world this ET-PEB could be exist please :D :D



#3 Sinphaltimus OFFLINE  

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Posted Wed Jan 10, 2018 6:28 PM

Correct me if I'm misunderstanding:

Assuming the GROM portion works in the end, this ET-PEB will incorporate:
SD used as Virtual Floppy Drives (FIAD or dsk or other or all?)
32k RAM expansion + 256K RAM (like a built in SAMS?SAMS Compatible?)
RS232 via USB
SD used as ROM/GROM loading like the FR99 and FG99 but without cartridges? 

Does that about sum it up? Just trying to understand everything you posted from a layman's perspective (mine).


Edited by Sinphaltimus, Wed Jan 10, 2018 6:28 PM.


#4 Shift838 ONLINE  

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Posted Wed Jan 10, 2018 6:46 PM

freakin' sweet!



#5 Vorticon OFFLINE  

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Posted Wed Jan 10, 2018 8:07 PM

Whoa! That would be so awesome!



#6 brain OFFLINE  

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Posted Wed Jan 10, 2018 8:16 PM

It looks like you're off and running, but on the off-chance you're looking for additional ideas or collaboration, I'm trying my hand at a similar project:

 

http://atariage.com/...cb-orientation/

 

I got sidetracked implementing GROM functionality in the CPLD and designing a 4MB-32MB MMU-based RAM sub-system with "MMU tasks", but I am readying a new board run.

 

JIm



#7 Opry99er OFFLINE  

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Posted Wed Jan 10, 2018 8:32 PM

Ooooooohhhhh.....

#8 adamantyr OFFLINE  

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Posted Wed Jan 10, 2018 8:48 PM

Cool to hear you want to support expanded memory!

I would say that if at all possible, you should use the same approach for paging memory that SAMS does so software will be fully compatible with it.

#9 LASooner OFFLINE  

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Posted Thu Jan 11, 2018 2:25 AM

bQSZbyB.gif


Edited by LASooner, Thu Jan 11, 2018 2:27 AM.


#10 speccery OFFLINE  

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Posted Thu Jan 11, 2018 6:30 AM

Oh Coool !! In my world this ET-PEB could be exist please :D :D

 

 

I did send the board to manufacturing, so the plain boards at least will exist. It will be interesting to see if I can make them work!



#11 speccery OFFLINE  

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Posted Thu Jan 11, 2018 6:44 AM

Correct me if I'm misunderstanding:

Assuming the GROM portion works in the end, this ET-PEB will incorporate:
SD used as Virtual Floppy Drives (FIAD or dsk or other or all?)
32k RAM expansion + 256K RAM (like a built in SAMS?SAMS Compatible?)
RS232 via USB
SD used as ROM/GROM loading like the FR99 and FG99 but without cartridges? 

Does that about sum it up? Just trying to understand everything you posted from a layman's perspective (mine).

 

Let me comment on these one by one:

  • SD used as virtual floppy drives, yes, at least in FIAD mode. This is something I have already done, albeit on a different architecture.
  • 32K RAM expansion will be part of the 256K. It would be two different modes of operation, depending on whether paging is on or not. When paging is disabled, you get the 32K RAM expansion, when paging is enabled you get 256K of paged memory. I haven't done the paging logic yet for this CPLD (Complex Programmable Logic Device), I just have the idea how to do it - and the working VHDL code for the FPGA implementation. But the FPGA has something like 100x the logic capacity... In fact the board has 512K of SRAM which can be divided to different functions by the logic chip. Some of the RAM is needed for ROM emulation to provide disk support etc, but this will not need a lot of space. In practice something like 450K could probably be available for paging from the viewpoint of RAM availability, but since the design will be constrained to how much logic can be put into he control chip, 256K is the likely scenario. SAMS compatibility would be the goal.
  • The board has two serial ports, both implemented by the the ARM micro controller. One of the is RS232 (but with 3.3V logic levels and only transmit and receive signals - no hardware handshaking). The other is serial port over USB (virtual COM port). The firmware (TI99 device driver, control logic and ARM code) will define how the ports would be exposed to TI software.
  • SD can be used for ROM and potentially also GROM loading, depending on how much logic fits into the control chip. 


#12 speccery OFFLINE  

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Posted Thu Jan 11, 2018 6:46 AM

Cool to hear you want to support expanded memory!

I would say that if at all possible, you should use the same approach for paging memory that SAMS does so software will be fully compatible with it.

 

I agree and this is my goal, but as I wrote above it depends on whether or not the necessary logic fits into the CPLD logic chip. For this board I tried to keep things simple (and cheap) so the logic chip has very limited capacity.



#13 Sinphaltimus OFFLINE  

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Posted Thu Jan 11, 2018 6:54 AM

Thank you for being one of the group keeping the TI alive, interesting and exciting with new hardware and projects.

 hope to own one of your FPGA consoles so I can add my own original keyboard and original case. 

I am definitely interested in this new project of yours. I may need to setup a third console when ready, simply to start playing with ram paging.

 

Good times. :)



#14 speccery OFFLINE  

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Posted Thu Jan 11, 2018 6:54 AM

It looks like you're off and running, but on the off-chance you're looking for additional ideas or collaboration, I'm trying my hand at a similar project:

 

http://atariage.com/...cb-orientation/

 

I got sidetracked implementing GROM functionality in the CPLD and designing a 4MB-32MB MMU-based RAM sub-system with "MMU tasks", but I am readying a new board run.

 

JIm

 

 

That's interesting. I had somehow missed that thread - it seems the last activity is from a year ago. January seems to be the month of new hardware every year...

 

The stacking idea is a nice one. I also thought about soldering the side port connector like you did, enabling horizontal installation, but for better or worse went with a vertical arrangement for this version. It is a prototype.

 

Your board seems to have the same XC95144XL chip. Is that the main programmable logic chip, or do you use others too?



#15 digdugnate OFFLINE  

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Posted Thu Jan 11, 2018 7:11 AM

following this thread with great interest. :)



#16 speccery OFFLINE  

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Posted Thu Jan 11, 2018 8:51 AM

I find it interesting that when I'm about to send a board to manufacturing (and this one was only my third board) I always find a bunch of important things to fix on the very last minute.

 

In this case I discovered that the pads on my board for the side port connector were too small. Before leaving for work in the morning I could not resist and quickly printed the board layout, taped that layout on a protoboard, and positioned a few components on it (SRAM, FLASH, side connector). I was happy to see that the SRAM and Flash fitted nicely, but the pads were small. Amazing that I did not notice this earlier. I did the layout very quickly, but I still having been staring at the pads of the connector for a while when routing the board.
Testing that components match the board layout before production

 

The other things I realised were that there will be no easy way to measure the RAM control signals during bring-up (added a 6 pin header) and that a few too many micro controller pins were not used in the design and were not going to be usable in the future as it is nearly impossible to solder wires to fine pitch components (added 3 test pads to some currently unused pins - at least it will be possible to solder wires to the test pads).



#17 adamantyr OFFLINE  

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Posted Thu Jan 11, 2018 11:05 AM

I'm very excited by this project! The NanoPEB's biggest issue was it was only able to provide the original 32K expansion. Being able to provide even a quarter of the memory the SAMS card has in the same manner will be a huge boon for programming projects.

 

Also, I love my peripheral expansion box, my birthday present from 1987, but even I worry that eventually it will break down and fail...



#18 brain OFFLINE  

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Posted Thu Jan 11, 2018 12:05 PM

That's interesting. I had somehow missed that thread - it seems the last activity is from a year ago.

Yep, my fault. At first, I had to search for more of the setup I have, since I am new to the platform. Finding the pieces took some time.  I also got slowed way down learning the platform, since I am not very familiar with the TI.  I spent some time designing a memory subsystem to fit the unit, and it led me to consider whether additional address lines on the "vertical bus" would be appropriate.  I will try to update the thread this week or next.

 

The stacking idea is a nice one. I also thought about soldering the side port connector like you did, enabling horizontal installation, but for better or worse went with a vertical arrangement for this version. It is a prototype.
 
Your board seems to have the same XC95144XL chip. Is that the main programmable logic chip, or do you use others too?

In this version, it is the only PLD, though I am considering other options.  I use Xilinx CPLD and FPGA devices, though I am not sure if I need a full FPGA on the primary PCB.


Edited by brain, Thu Jan 11, 2018 12:12 PM.


#19 unhuman OFFLINE  

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Posted Thu Jan 11, 2018 8:59 PM

If someone could make one of these that fit inside the speech synthesizer (with the speech synthesizer) that'd be the absolute best.  I'll buy one.  And, I'd buy one even if it doesn't.


Edited by unhuman, Thu Jan 11, 2018 8:59 PM.


#20 Schmitzi OFFLINE  

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Posted Fri Jan 12, 2018 3:41 AM

yes, "PEB-in-da-Speech" would be nice ;)  :D 



#21 acadiel OFFLINE  

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Posted Fri Jan 12, 2018 6:55 PM

Yep, my fault. At first, I had to search for more of the setup I have, since I am new to the platform. Finding the pieces took some time.  I also got slowed way down learning the platform, since I am not very familiar with the TI.  I spent some time designing a memory subsystem to fit the unit, and it led me to consider whether additional address lines on the "vertical bus" would be appropriate.  I will try to update the thread this week or next.
 
In this version, it is the only PLD, though I am considering other options.  I use Xilinx CPLD and FPGA devices, though I am not sure if I need a full FPGA on the primary PCB.


If you need to borrow anything at VCF-SE, let me know and I’ll bring it. I have lots of hardware goodies. :)

#22 acadiel OFFLINE  

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Posted Fri Jan 12, 2018 9:56 PM

Darn impressive.  We're amping up our TI's like we're going to have exoskeletons one day :)



#23 speccery OFFLINE  

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Posted Sat Jan 13, 2018 3:05 AM

If someone could make one of these that fit inside the speech synthesizer (with the speech synthesizer) that'd be the absolute best.  I'll buy one.  And, I'd buy one even if it doesn't.

 

 

Once the design is right (schematics + parts) doing another board layout is just some additional work, so this would be interesting. Having the speech synthesiser in there simultaneously would be a lot harder. Perhaps the ET-PEB board could be on the bottom, connecting to the the side port, and there could be a stacked new board with the original TMS5220 chip and the two TMS6100 ROMs on top.



#24 speccery OFFLINE  

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Posted Sat Jan 13, 2018 3:12 AM

I'm very excited by this project! The NanoPEB's biggest issue was it was only able to provide the original 32K expansion. Being able to provide even a quarter of the memory the SAMS card has in the same manner will be a huge boon for programming projects.

 

Also, I love my peripheral expansion box, my birthday present from 1987, but even I worry that eventually it will break down and fail...

 

There are 2megabyte SRAM chips in the same TSOP 44 pinout (with two more address lines, IS61WV20488BLL chips http://www.issi.com/...1-64WV20488.pdf) so that would facilitate the full 1 megabyte of SAMS RAM + plenty of space for DSRs, ROMs and the like. I now realise I did not route those two extra address lines from the CPLD to the RAMs... Something I forgot as I was eager to get the boards to production, but perhaps adding manually two wires is within the realm of possibility. Quickly checking it turns out that A19 and A20 address pins at the ends of the side of the RAM chip, the adjacent pins are unconnected on one side, so manually adding that support to this first board is possible if there are enough macrocells free in the CPLD to support that.



#25 Vorticon OFFLINE  

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Posted Sat Jan 13, 2018 6:33 AM

With the I2C and USB ports, this thing will be an incredible platform for experimentation and interfacing. I really hope it comes to fruition.






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