Over the weekend I turned my attention from the ET-PEB hardware debugging to software. The hardware will need more testing, but I am waiting for the new PCBs to arrive before continuing extensive hardware testing - there is plenty of work on the software side too. Also the hardware has been getting stable enough for software development.
By the way, one small learning for me was that it would be beneficial to keep the dimensions of the PCB under 10cm per side - the new PCB is now over 10cm long while a lot narrower, but going over 10cm in either direction means a bit more cost. Well, this is still prototyping - and learning along the way. I actually quite enjoyed doing the board layout - so I will probably do yet another one after debugging/testing the new boards. I may switch to micro SD cards to reduce board size. I will also remove the debug headers and maybe even the JTAG header for the CPLD, as my plan is to implement the CPLD programmer in the MCU. That will make the board much more versatile and also reduce size.
On the software side I had some time during the weekend to work on the DSR and microcontroller code to build SD support. I have had some legacy code from my FPGA project, where the PC acted as a file server for the TI-99/4A. That code base was influenced by Tursi's great work on Classic99 and actually reused a portion of that code. But now, running the SD card FAT/FAT32 filesystem on the microcontroller side I had to rewrite pretty much all the code to support a different memory model, since the microcontroller has very limited RAM and Flash ROM. After quite a few attempts and bug fixes I did get it working. My test case has been running the Editor/Assembler cartridge (off FinalGROM99) and testing loading and saving editor files in both variable and fixed record file formats, as well as compiling Matthew's YING assembler program using the ET-PEB as the memory expansion and mass storage device.
I got all of this to the point where I have been able to make my test case work, in other words E/A works, it is able to load the editor program to expanded memory, as well as the assembler. The assembler was able to compile and produce working binary files (i.e. tagged TI object code), as well as listing files, so this is getting to a nice level of functionality. I did get bitten (again) by the fact that the E/A cartridge does not care to close the source files before using the same "file handle" i.e. VDP memory address again for another file. I fixed that by just special casing this behaviour - if an already open file handle is being used again for another open command, the micro controller will close automatically the previous file before opening the new file.
To summarise, the ET-PEB now supports
- Saving and loading DSR operations (tested with saving and loading short basic programs and loading of binary files)
- Open/Close/Read/Write/Restore DSR operations on record based files, such as the ones produced and consumed by the E/A cartridge. I've tested both fixed and variable length records to the extent used by E/A.
- Mapping of DSK1/DSK2/DSK3 to separate directories on the SD card. Files are stored with TIFILES 128-byte headers
- 32K memory expansion (standard non-paged memory expansion)
- 256K SAMS style paged memory (only tested by running the AMSTEST4 program many times, which repeatedly succeeds)
There are still some lacking features, for instance it is not yet possible to open DSK1. to enumerate the files on the disk. From where I am at the moment adding that support is not hard.
One challenge I am facing now is that the 32K Flash memory of the microcontroller is pretty much used up, I have a few hundred bytes left. My code has a lot of debug print statements, and removing those will save perhaps one or two kilobytes of code space, but it will be a squeeze. I will probably move over to the LPC1347 chip, which is pin compatible but has 64K of Flash, to give some breathing room. Despite being pin compatible this chip has a somewhat different set of peripherals on board, meaning that for example the general purpose I/O control registers and pin configuration in general needs to be setup differently. So there is a bit but not much porting work to be done to support this chip.
Edited by speccery, Tue Feb 27, 2018 3:43 PM.