Did some work on the ET-PEB, finally there was some time. I've been now working on the LPC11U37 powered ET-PEB, which is good for development since there is plenty of Flash memory, but I have to say that the speed difference between Cortex M0 (LPC11U37) and Cortex M3 seems much greater than the clock speed difference would suggest... Well it is still pretty fast, and gcc works so the source code is pretty much the same.
I worked on a couple of things:
- Implemented "full" support for SUBLNK 0x14 to provide sector based access to file reading. The code is getting a bit messy as there now are three different methods of loading data from files: the DSRLNK opcode LOAD, DSRLNK opcode READ, and SUBLNK read sector. I will need to try to unify the code, but I have to say that the TI guys did not really do a great job when defining the disk interfaces. The sector based SUBLNK 0x14 is perhaps the best interface...
- With the above support I was able to run adamantyr's AMS test program successfully. I thought it was a test program, but it actually is a game
- Implemented a mount command which allows DSK1,2 and 3 to point to different directories on the SD card than just DSK1, DSK2 and DSK3.
With those changes the disk support is slowly getting readier. I still need to implement a couple DSRLNK opcodes (namely DELETE and STATUS) and the remaining SUBLNK opcodes. Some of the SUBLNK opcodes don't really make sense in my setup, since I am not supporting disk images (at least yet), only files on disk, so direct sector reading/writing operations or formatting do not make sense.
By the way, one potential advantage of the ET-PEB when compared to other disk systems is that it does not use any VDP RAM for disk buffers. Obviously to comply with TI specs the reads and writes put data to VDP RAM, but a FILES(x) command is not needed, since VDP RAM is not reserved for any ET-PEB operations. In other words the TMS9900 side DSR does not need any VDP RAM. The disk operations use the RAM of the microcontroller, and if I run out of that I have over 200K RAM available on the external RAM chip. Accessing that RAM from the micro controller is a bit like the TMS9900 talking to the VDP, as I have first have to setup the address on the CPLD before a read/write operation can take place. I can probably optimise those accesses further if needed, currently I seem to be getting about 100K bytes/s of bandwidth to the external RAM (shared with the TMS9900 - so care is needed). At this point of development that is not critical. It is worth noting that with a custom software interface the micro controller could stream data from the SD card to the RAM expansion of the TMS9900 with no CPU intervention.