Fitting the test
So, after a fair amount of struggle to get the board routed out (in the end I'm going to get a third-party router for Eagle called Electra), I've got to the stage where I have a candidate for the final board. I'm going to talk to a different bunch of guys at work next week (I'm back in on Wednesday) to make sure I've not screwed up the layout too much I'm thinking I might post it on reddit for review as well - the more eyes the merrier.
Here's what it currently looks like.
There's been a couple of tweaks since the last time I posted, which came out of the second design review. The main issue they had with the design was a power-rail problem. I'd gone with using gated LDOs for the 1.0v, 1.8v, and 3.3v power rails for the FPGA, all sourced from the 5v power plane. The problem was that, with a voltage drop from 5v to 1v and a power requirement of 2A, the LDO would be sinking 8W in heat. That's a lot.
The solution was to drop the LDO approach and use a switching power supply - these are far more efficient because they're either conducting 100%, or not conducting at all. In neither state do they generate much waste heat, in contrast to a linear LDO which effectively dumps all the extra energy (when going from high voltage to low) into an internal resistance, producing a lot of heat.
Generally I find that engineering a switching regulator circuit is a lot harder than a (relatively simple) LDO. Fortunately, TI have something called 'Webench power designer' which allows you to type in your fixed parameters and it'll come up with solutions (TI-based, obviously). You can even do Spice simulations of the circuit in the browser, and if you can't source one of their first-choice parts, you can click on it and it offers options from different manufacturers. This made creating the power circuits pretty simple
While doing that, I figured it'd be easier to have a single 3.3v rail, since the switchers are available at fairly high amperage, and it simplified the board layout as well. So now there's a 10A 3.3v rail which goes directly onto an internal continuous 3.3v plane via lots of vias (pardon the pun). Likewise, there are plenty of vias for the ground plane so the return path is unencumbered. I also added copper pour around the input jack, so power can dissipate into the GND, +3V3 planes either from the connection to the inner-plane directly, or via the copper pour and then the vias to the inner-plane. The idea is to keep the path from wall-wart to power plane as low resistance as possible.
I also added ground-loop bounce capacitor-pairs along the border of the 5v plane, so that long ground loops couldn't form as signals traversed across the 5v plane boundary.
Now the FPGA is using the same +3V3 plane as the rest of the board, there's no need to route out to the VCCO lines, they just sink a via and get their power, which is nice, but for VCCINT and VCCAUX, I routed a polygon on an inner plane so that they could do the same.
The power budget on the 3.3v rail is about 1A for the CPU, about 1.5A for the FPGA, and about 0.5A for everything else put together. This leave me with 1A per slot and a comfortable overhead remaining of ~3A. Ideally, with modern electronics, a slot shouldn't require 1A of power, it ought to be in the low hundreds of mA at best, but it's there if it's needed.
The other issues raised in the design review were of lesser importance (adding 0R resistors rather than direct connections to power or ground, for example), and I've gone through and made those changes.
Apart from that, there were a few cosmetic changes
- I rotated the SDRAM - I ought to have done this earlier, it makes access to the pins far easier.
- Removing those six 3.3v regulators made some space on the board, so I could move around the cartridge and serial port a bit, making more space for the power region below.
- I added a dip-switch for the FPGA configuration mode. Apparently it can be useful to be able to force the FPGA into JTAG configuration mode, rather than SPI-master.
- The FPGA SPI flash can be written to by both the FPGA and the CPU, but the FPGA wants to be able to read it at a high frequency (about 50 MHz, in Quad-SPI mode), so there are rules about signal integrity and not having spurs etc. The solution was to use an analogue mux, switchable by the CPU, but by default allowing access to the FPGA, which preserves the point-to-point connection that the FPGA wants, but allows the CPU to override it to create a point-to-point connection to the CPU instead.
- I went through and made sure the labels were correct and appropriate, so the board is "ready to go" once I decide to pull the trigger.
Testing the fit
I also got back the test board from Seeed and the cartridge port now fits perfectly. It looks as though the USB-c connector will be good too, but I'm waiting on Digikey to deliver the part before I can claim that. The SD-card connector seems to be a good fit, and the same Digikey shipment will allow me to test the VGA connector.
The only issue with the Seeed board was that the power connector wouldn't fit, the holes for the pins were too small, it looks as though they don't like items on the 'milling' layer. I could, however, fit the power-jack pins into the holes for the VGA connector, so I've altered the footprint for the power jack to have larger holes, and deleted the milling information. That ought to make it work on the real board.
Whew! I think that's about it for today