It's very encouraging that we now have more people creating interesting projects in VHDL for the TMS9900 systems, thanks for all the efforts pnr!
I am interested in computer architecture in general, and having a small TMS9900 based self-contained system for FPGA will be indeed be a great platform for further development. This design at least is very well understood by us.
Once we get the breadboard project as you described above running, I am interested in how performance can be pushed forward. I know this is not perhaps an interesting direction for everyone, but I am interested in creating the fastest TMS9900 system we can make. This is really for personal interest, as there is no existing software that could take benefit of a much higher performance:
- I'm very keen to try out how many TMS9900 cores I can cram into the FPGA. The dual ported RAMs of the FPGAs allow sharing internal ROM memories between two cores, without wasting memory blocks, so multicore implementations can be interesting in many ways.
- With the serial port as a channel to outside world, the rest of the logic can be clocked to higher clock frequencies than in my TI-99/4A design. It will be interesting to see how high the clock frequency can be for the CPU core.
- An additional direction I would like to try is to implement a cache memory for my TMS9900 core using two memory blocks (one for data, one for address tags for a simple direct mapped cache structure). This again would help in multiprocessor system, as each core could have its own local cache, and they could interface to an external memory over a shared bus.
With regards to pnr's TMS9902 design, a practical extension could be the addition of a receive FIFO, for example a 16550 style 16 byte FIFO. This could probably be done in a transparent way so that software would not need changes. Having said that I don't know if the bandwidth of TI-99/4A serial communication software is constrained by lost characters, or perhaps other things, or even if bandwidth is/has been an issue.