Jump to content

Photo

VHDL for a 9902

9902 vhdl

55 replies to this topic

#51 speccery OFFLINE  

speccery

    Moonsweeper

  • 335 posts

Posted Tue May 1, 2018 12:28 PM

It's very encouraging that we now have more people creating interesting projects in VHDL for the TMS9900 systems, thanks for all the efforts pnr!

 

I am interested in computer architecture in general, and having a small TMS9900 based self-contained system for FPGA will be indeed be a great platform for further development. This design at least is very well understood by us.

 

Once we get the breadboard project as you described above running, I am interested in how performance can be pushed forward. I know this is not perhaps an interesting direction for everyone, but I am interested in creating the fastest TMS9900 system we can make. This is really for personal interest, as there is no existing software that could take benefit of a much higher performance:

  • I'm very keen to try out how many TMS9900 cores I can cram into the FPGA. The dual ported RAMs of the FPGAs allow sharing internal ROM memories between two cores, without wasting memory blocks, so multicore implementations can be interesting in many ways.
  • With the serial port as a channel to outside world, the rest of the logic can be clocked to higher clock frequencies than in my TI-99/4A design. It will be interesting to see how high the clock frequency can be for the CPU core.
  • An additional direction I would like to try is to implement a cache memory for my TMS9900 core using two memory blocks (one for data, one for address tags for a simple direct mapped cache structure). This again would help in multiprocessor system, as each core could have its own local cache, and they could interface to an external memory over a shared bus.

With regards to pnr's TMS9902 design, a practical extension could be the addition of a receive FIFO, for example a 16550 style 16 byte FIFO. This could probably be done in a transparent way so that software would not need changes. Having said that I don't know if the bandwidth of TI-99/4A serial communication software is constrained by lost characters, or perhaps other things, or even if bandwidth is/has been an issue.



#52 Ksarul ONLINE  

Ksarul

    River Patroller

  • 4,568 posts

Posted Tue May 1, 2018 4:59 PM

At one point several years ago, there was a website up that showed a 9900-based parallel computer using 16 TMS-9900 CPUs, each on its own circuit card with memory and IO on each card. Unfortunately, the last time I went looking for the site, it was gone. I haven't checked to see if the Wayback machine captured it though. . .so I'll have to look to see if I still have the URL.


  • RXB likes this

#53 jens-eike OFFLINE  

jens-eike

    Star Raider

  • 81 posts

Posted Wed May 2, 2018 11:29 AM

At one point several years ago, there was a website up that showed a 9900-based parallel computer using 16 TMS-9900 CPUs, each on its own circuit card with memory and IO on each card. Unfortunately, the last time I went looking for the site, it was gone. I haven't checked to see if the Wayback machine captured it though. . .so I'll have to look to see if I still have the URL.

 

http://www.famkoplien.de/henry/TI99/



#54 Ksarul ONLINE  

Ksarul

    River Patroller

  • 4,568 posts

Posted Thu May 3, 2018 4:25 AM

That's it. There was also an earlier version of the page that went into a lot more detail on the system.



#55 RickyDean OFFLINE  

RickyDean

    Dragonstomper

  • 825 posts

Posted Thu May 3, 2018 6:22 AM

That's it. There was also an earlier version of the page that went into a lot more detail on the system.

I just looked at the wayback machine, the only entry for this web url is in 2016 on June 4th. Maybe there was another web page showing this system.



#56 speccery OFFLINE  

speccery

    Moonsweeper

  • 335 posts

Posted Sat May 19, 2018 12:24 PM

A little off topic - discussing the "breadboard" design which incorporates my TMS9900 CPU core with pnr's TMS9902 UART and Stuart's Cortex Basic port. It is a speedy system, with the CPU running at 100 MHz. The Cortex Basic is a fast Basic to begin with on the TMS9995 which was the original CPU for it. The design is inspired by and based on Stuart's very nice breadboard systems.

 

I updated the git repository and wrote a bit more informative README file  - with pictures :)

 
So now the breadboard design is ported to three different FPGA boards, more information provided at the README file which you can immediately see by clicking the link. 
They all perform identically as only on-chip resources (memory) are used.
 
What is very interesting, is that on the Altera EP4CE22 the system only takes 9% of the LUTs. So now I really want to shrink the usage of on-chip memory, and put in many CPU cores. There are two ways to use external memory: the obvious thing is to use the SDRAM, but that does not work on the Mini board as there is no SDRAM. However, that board has a whopping 8 megabytes of SPI flash. So my plan is to implement an interface a simple system where the TMS9900 can run code directly off the SPI ROM. Sure, that will be pretty slow, but it will be interesting. On the Pepino FPGA board's site one of the example projects does this (it is a Mac clone). The Mac implementation runs 68000 code off SPI, but on the Pepino the SPI is wired in quad mode, so it actually achieves very high transfer rates in bursts. In QPI mode the data transfers are serial but 4 bits at a time, and running at something like 50MHz.
 
Anyway all the more reason to add caching… And to find a way to run the Cortex Basic with minimum RAM. I haven’t had time to work on it.






Also tagged with one or more of these keywords: 9902, vhdl

0 user(s) are browsing this forum

0 members, 0 guests, 0 anonymous users