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SRL by 8 vs SWPB timing


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#1 FarmerPotato OFFLINE  

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Posted Thu May 3, 2018 11:02 AM

I have been finding this in ISR code and I am wondering how wasteful it is in cycles? Would someone who knows TMS9900 timing care to analyze it?
All registers are in external RAM (full wait state penalties).
 
movb  *r8,r8
srl   r8,8
 
Proposed Optimization:
 
clr r11
movb *r8,r11
swpb r11
 
The programmer has RUN OUT of temp registers and is overusing R8, but I see R11 is free.
 
Thanks in advance!
 


#2 mizapf OFFLINE  

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Posted Thu May 3, 2018 11:37 AM

On the 9900, SWPB uses 10 clock cycles plus memory cycles, while Shifts use 12+2c cycles with c=shift count, plus memory cycles.

 

Interestingly, on the 9995, the SWPB uses 13 cycles, while the Shifts use 5+c cycles.



#3 Lee Stewart ONLINE  

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Posted Thu May 3, 2018 12:28 PM

Perhaps:

CLR  R11
MOVB *R8,@1(R11)

[Edit: As pointed out later by mizapf and FarmerPotato, the above will not work.  Rather, the address of the current workspace would need to be copied to another register—say, R13—and the offset of the LSB of R11 added:

STWP R13
CLR  R11
MOVB *R8,@23(R13)

Thanks, guys.]   :)

 

...lee



#4 mizapf OFFLINE  

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Posted Thu May 3, 2018 12:43 PM

Perhaps:

CLR  R11
MOVB *R8,@1(R11)

...lee

 

 

That would mean to copy the byte at the address pointed to by R8 to address >0001. Maybe you had a STWP in mind?



#5 Asmusr OFFLINE  

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Posted Thu May 3, 2018 12:48 PM

With r8 = >a000 and workspace in >8300:

movb *r8,r8                 (26)
srl  r8,8                   (32)
                            (58)
   
clr  r11                    (14)
movb *r8,r11                (26)
swpb r11                    (14)
                            (54)

clr  r11                    (14)
movb *r8,@>8317             (38)
                            (52)


#6 FarmerPotato OFFLINE  

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Posted Thu May 3, 2018 1:08 PM

 

 

That would mean to copy the byte at the address pointed to by R8 to address >0001. Maybe you had a STWP in mind?

I can work with that.. There is already a STWP which I can keep around in R13.  

 

STWP R13   this is already paid for

CLR   R11

MOVB *R8,23(R13)    to low byte of R11

 

 

Based on Rasmus' cycle counts, this is at best slightly faster.  (Note: registers are in external ram >D844)

 

I see this code 2 times, so I consider

AI R13,23   point to R11 lsb

Then each time

MOVB *R8,*R13

I can take care that the high byte of R11 will stay 0.



#7 Lee Stewart ONLINE  

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Posted Thu May 3, 2018 3:49 PM

That would mean to copy the byte at the address pointed to by R8 to address >0001. Maybe you had a STWP in mind?

 

That one trips me up a lot.  Obviously, the register in () would need to contain the address of R11—doh!  :dunce:  And—of course, STWP would get the address of R0.  Thanks, mizapf.

 

...lee






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