ThomH Posted May 12, 2018 Share Posted May 12, 2018 Per the SN76489 data sheet, it needs 4 cycles to load a data value. I note from the schematic that its ready line is connected to the Z80's WAIT input. I notice that the Z80 OUT will have been asserting the write input for 1.5 cycles before it tests WAIT. So it looks to me like it should end up inserting three WAIT cycles, making the entire machine cycle seven cycles long. Or, in net, adding three cycles to any OUT that is decoded to access the SN76489. Is that a correct reading? Quote Link to comment Share on other sites More sharing options...
ThomH Posted February 28, 2019 Author Share Posted February 28, 2019 In case anybody finds this in the future; I had failed to spot the divide-by-eight that precedes the four-cycle number. So the conclusion posited above is incorrect. See http://atariage.com/forums/topic/286986-m1-delay/ for real discussion of this topic. Quote Link to comment Share on other sites More sharing options...
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