When would reads from Suzy take 15 cycles?

[ThomH]

To quote the Epyx documentation, potential 16Mhz cycle counts for 65C02 actions are:

 

 

Cycle Min Max
---------------------------------------------------
Page Mode RAM(read) 4 4
Normal RAM(r/w) 5 5
Page Mode ROM 4 4
Normal ROM 5 5
Available Hardware(r/w) 5 5
Mikey audio DPRAM(r/w) 5 20
Mikey color palette DPRAM(r/w) 5 5
Suzy Hardware(write) 5 5
Suzy Hardware(read) 9 15

 

Those all make sense to me, even if some are slightly vaguely documented, except Suzy reads potentially taking 15 cycles. It's been a very long time since I did any Lynx programming so please jump directly upon any of my logic faults.

 

The CPU has the bus, so Suzy is not drawing. So we're not talking about 9–15 cycles spent trying to intersect with sprite activity. The only other thing Suzy does is maths, but that's asynchronous rather than blocking. One uses SPRSYS to check for completion if it can't just be assumed.

 

There is some reference to Suzy having to cede the bus to Mikey for video DMA, but that feels like a distinct issue since Mikey obviously can get at the frame buffer while the CPU is happily doing its own work at 4 or 5 cycles per tick?

 

I feel like I'm failing to make a necessary mental connection.

[enthusi]

Isnt the issue at least for audio that the registers are rotating?

I recently wondered the same and just throw this in for discussion and would love to learn about this as well

[ThomH]

Isnt the issue at least for audio that the registers are rotating?

I recently wondered the same and just throw this in for discussion and would love to learn about this as well

 

 

I think that explains the 5 min and 20 max on Mikey — presumably the options are exactly 5, 10, 15 or 20 depending on whether you have to wait 0, 1, 2 or 3 rotations for your channel to come around.

 

Luckily, I discovered the answer elsewhere in the documentation, seconds ago! It's cartridge reading:

 

 

 

9.2 ROM Cart Data Read

...

When a read request comes from MIKEY, Suzy will hold off MIKEYs DTACK, enable the ROM (which overdrives any pressed switches), wait 437.5 ns (for ROM access time), and disable the ROM. Towards the end of the wait, SUZY passed the data from the ROM to Mikey and released the DTACK. The actual access time available at the pins of the Cart is 392ns. The CPU cycle that performed the actual read uses 15 ticks of the clock.

 

RCART is at FCB2 and FCB3, so despite there being co-ownership of the actual task it's within Suzy's address space. So I think it counts as reading from Suzy.

[enthusi]

Ah, interessting. Thanks!