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ABBUC hardware contest entry: Pokeymax

abbuc hardware pokey replacement chip fpga

47 replies to this topic

#26 antrykot OFFLINE  

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Posted Fri Aug 24, 2018 1:31 AM

 

At the first write to pokey2, it will indicate it's a stereo signal. Then right and left channels are different (State 1).

 

OS writes to pokey2 during system initialization.



#27 foft OFFLINE  

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Posted Fri Aug 24, 2018 2:30 AM

 
OS writes to pokey2 during system initialization.


I wonder if it only writes a few known values (0x00 and 0xff perhaps) when it does the hardware reset. Could exclude those.

Another option would be to mix left/right to both outputs, with a volume adjustment to the other channel.

#28 flashjazzcat OFFLINE  

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Posted Fri Aug 24, 2018 5:42 AM

I think the most reliable method is to allow stereo toggling via U1MB as already suggested, and also offer a physical method of disabling the second POKEY (i.e. a switch header) for those not using Ultimate, and to only send the left POKEY to both channels in mono mode.

 

Note that in order for Ultimate 1MB to correctly identify a second POKEY using the default plugin, the IRQ line on the second chip must be unconnected, even when the second POKEY is on the bus. If the second POKEY IRQ is required, however, it would be wise to put this under software control as well (via U1MB, for example). The 1088XEL U1MB BIOS plugin is able to handle dual POKEYs and toggle the second POKEY IRQ.

 

Enabling IRQs on the second POKEY generally appears to result in a lot of crashes, however, so it's probably not worth bothering with. I have no idea what the intention was there, but I thought it worth mentioning.


Edited by flashjazzcat, Fri Aug 24, 2018 5:44 AM.


#29 mytek OFFLINE  

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Posted Fri Aug 24, 2018 10:09 AM

The intention of having a switchable 2nd IRQ was aimed at more fully utilizing the 2nd Pokey's hardware (i.e., internal counters), but in reality perhaps not worth the effort or the sacrifice of one of the limited U1MB I/O bits. This is what happens when trying to please other's request for such, without fully exploring the logic of doing so, and/or running tests to truly play out the scenario. I would love to turn back time and take a different direction regarding this in the 1088XEL, but for better or worse what's done is done.

I agree with keeping the audio switching logic same as done with a Lotharek U-Switch in combination with his simple stereo board, as mimicked in the TK-II-Stereo or 1088XEL boards. So we are talking about a TTL input that has a logic High = Stereo, logic Low = Mono.

#30 ivop OFFLINE  

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Posted Fri Aug 24, 2018 11:44 AM

I was the one asking for the 2nd IRQ optionally to be connected. The idea was that one could run four 16-bit timer interrupts to play samples at varying rates simultaneously. We also aligned the SIO pins with my MIDI project, except that afterwards Audio IN was added and is not present on the 1088XEL SIO pin header. This could be added for the 1088XLD. Or you could integrate the complete MIDI interface, incl. a Waveblaster port ;) :D



#31 mytek OFFLINE  

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Posted Fri Aug 24, 2018 12:44 PM

I was the one asking for the 2nd IRQ optionally to be connected. The idea was that one could run four 16-bit timer interrupts to play samples at varying rates simultaneously. We also aligned the SIO pins with my MIDI project, except that afterwards Audio IN was added and is not present on the 1088XEL SIO pin header. This could be added for the 1088XLD. Or you could integrate the complete MIDI interface, incl. a Waveblaster port ;) :D

 

Opps didn't mean to rain on your idea (I had forgotten who asked for it), and at the time it did seem like a good one. But I suspect it'll be a little used aspect which ended up causing a bit of grief when Jon and I were working together on a way to test for it in a conclusive way that didn't interfere with other stuff running in the background. However the loss of a control bit to enable or disable it, might have been a sacrifice that never gets justified. Because it seems like more and more upgrades are beginning to compete for U1MB control.

 

The 1088XLD project does have left and right audio inputs on a header pretty close by the SIO-AUX header labeled for P-COVOX use, but could just as easily be connected to your MIDI design. On integration of the MIDI into the XLD, there really is limited space if I don't layer stuff like on the XEL, which I have been trying to avoid. Although there currently is a big empty spot under the U1MB that could easily accommodate it, so I may reconsider  ;) .



#32 Mathy OFFLINE  

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Posted Fri Aug 24, 2018 6:38 PM

Hello guys

 

Has anybody ever tried to find out why using the second Pokey's IRQ are causing problems?

 

Sincerely

 

Mathy

 

PS if somebody did, a link will suffice.



#33 mytek OFFLINE  

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Posted Fri Aug 24, 2018 6:56 PM

Hi Mathy,

 

For the most part having the 2nd IRQ present doesn't cause any issues. However some applications for whatever reason must inadvertently activate this IRQ causing a crash (i.e., Yoomp!). So that's the reason for being able to disable it, which is what is supported in the 1088XEL and the XEL version of the U1MB Bios. I guess the tricky part in actually making use of it comes down to not having support for this particular IRQ in the stock OS. The present OS has no awareness of this IRQ, or a method to deal with it. So this probably means it can't be used from something like a Basic program without having the system lock up.



#34 Level42 OFFLINE  

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Posted Fri Aug 24, 2018 6:59 PM

Deleted

Edited by Level42, Fri Aug 24, 2018 7:16 PM.


#35 flashjazzcat OFFLINE  

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Posted Fri Aug 24, 2018 11:28 PM

The OS hangs when it tries to dispatch an IRQ it has no method of acknowledging, I guess.

#36 foft OFFLINE  

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Posted Sat Aug 25, 2018 12:39 AM

Well I didnt connect the IRQ for the second pokey. When I make the updated revision for production I should break out a few more io pins.

Edited by foft, Sat Aug 25, 2018 12:39 AM.


#37 _The Doctor__ ONLINE  

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Posted Sat Aug 25, 2018 1:02 AM

whatever you don't use, leave a connection point, who knows if something comes along for it later as people explore and make  :)



#38 foft OFFLINE  

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Posted Sat Aug 25, 2018 1:45 AM

whatever you don't use, leave a connection point, who knows if something comes along for it later as people explore and make  :)


Well there are about 100 spare io pins but there isnt much room:) I wanted it on a single sided 2 layer pcb.

#39 Level42 OFFLINE  

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Posted Sat Aug 25, 2018 2:02 AM

The music in Kaboom sounds pretty spot on. :)

I agree....but Kabooms music is not exactly pushing POKEY to its limits.... :D

The response of the paddles (no lag) is the important factor of this demo I guess and it looks to be no problem at all, but can only tell once I feel it...but I see little reason why tPokemax would be slower than a real one.

Does it also handle high SIO bitrates ? This is very important for sure.

I would strongly urge you to have someone with an arcade machine with POKEY(s) on it do some testing with Pokeymax.
A good machine would be Star Wars as a dedicated 6809 controls 4 POKEYs (plus a TI voice synth). IMHO Star Wars pulled the most out of the POKEY when it comes to advanced music and sound when it comes to the arcade machines using POKEY.

Sadly I sold mine a few years ago, along with all the other machines. Another good machine to test it on is Centipede. Centipede doesnt have a separate processor to control POKEY and since a defective POKEY has some distinct effects on the machine it might show up any incompatibilities,

If SW owners could put in two POkeymaxes instead of 4 POKEYs.....they might like that of course....

Do note that Star Wars sound is NOT stereo. It does sound like it, especially in the cockpit machine, but its fake stereo, the sound is simply produced directly in one speaker and a bit time shifted in the other, its an old trick also used on some audio hardware BITD (stereo expander).
This is fully done in hardware external of the POKEYs though, so you dont have to worry about that....
. The effect it pretty strange, but effective.

Anyway, Id have to dig up my Star Wars schematics to excacly know how POKEYs are tied in on the dedicated soundboard of SW.

If you dont have any contacts in the arcade collecting scene I still do and I know where my machines went and Im sure he would be willing to give Pokeymax some test runs.

Really, the arcade scene is definitly a good market for a good POKEY replacement but its the only market that might use POKEY in a slightly different way compared to our beloved Homecomputers do :)
Mostly though, POKEYs merely create rather simple sounds on most Atari arcade machines, the coin-op devision guys werent exactly far into pushing POKEY to its limits, then again, neither was any A8 software at that time (1980-1983).

but it would be a shame to not serve our felllow arcade collecting friends...some of them might be on this forum too.

Edited by Level42, Sat Aug 25, 2018 2:10 AM.


#40 foft OFFLINE  

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Posted Sat Sep 8, 2018 2:07 PM

I've just finished the PCB layout for the friend of PokeyMAX. Its called DigiMAX and is really just 40 pins connected to the MAX10 FPGA via 3.3V/5V level shifters. Which I'm hoping will work for ANTIC, GTIA and Sally replacements with a little effort on the VHDL. Useful, maybe not, but I'm sure it'll be fun to try! 



#41 Irgendwer OFFLINE  

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Posted Sat Sep 8, 2018 3:46 PM

 Which I'm hoping will work for ANTIC, GTIA and Sally replacements with a little effort on the VHDL. Useful, maybe not, but I'm sure it'll be fun to try! 

 

An upgraded version of Sally would be very interesting. A 100% ("illegal"-) op-code compatible CPU replacement with turbo mode

(I already wrote that in another thread but for completeness again):

 

* A "special" instruction sequence enters turbo mode

* in turbo mode most single byte instruction take only a single cycle (e.g. INY, CLC, ROL)

* branches could be one cycle faster if taken as well as page breaking indirect accesses

* the zero-page RAM resides inside the CPU replacement, so that the zero page bus cycle is saved and could take place even if CPU is halted by antic

* additional useful instructions are added on the places where the unstable "illegal instructions" reside

* it could also make sense to support the stack area inside the CPU replacement, saving the external bus cycles for stack operations (imagine a single cycle "RTS")

 

The drawback is only a moderate acceleration (I guess about 20-30%), but the quite high compatibility (as it is unusual to let ANTIC access the zero-page or stack) and simple plug-in installation would be IMHO very interesting anyway.

 

It could maybe be possible to switch also to the 65C02 instruction set.



#42 ivop OFFLINE  

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Posted Sat Sep 8, 2018 5:41 PM

Or a 8080/Z80. And run CP/M.
Or a 6809 and run NitrOS-9, similar to this

 

 



#43 IndusGT OFFLINE  

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Posted Sat Sep 8, 2018 8:29 PM

To answer some questions:
1) mono version: the price would not change much and the current one works as mono if A4 is simply not connected.
2) Total price: TBD, will depend very much on quantity. The more, the cheaper. These ones cost me about 40usd but it was a small prototype run and I had to make the pcbs twice due to a mistake.
3) Auto right channel=left channel: Very doable, would have to come up with a way of detecting. No writes to pokey2 in 30 seconds and no audio out perhaps?
4) Compatibility: Well even Commodore couldnt make sid match sid exactly! I think its pretty good but it isnt the original chip. Im sure emkay will help me find things to fix:)
5) Stereo switch via Ultimate mb: I guess this is easy, does it output lvttl levels?
6) JHV: No plans but I could be convinced!
7) Video: Ill make one.

Any chance of this having Covox  ?



#44 Kyle22 ONLINE  

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Posted Sat Sep 8, 2018 11:38 PM

 

An upgraded version of Sally would be very interesting. A 100% ("illegal"-) op-code compatible CPU replacement with turbo mode

(I already wrote that in another thread but for completeness again):

 

* A "special" instruction sequence enters turbo mode

* in turbo mode most single byte instruction take only a single cycle (e.g. INY, CLC, ROL)

* branches could be one cycle faster if taken as well as page breaking indirect accesses

* the zero-page RAM resides inside the CPU replacement, so that the zero page bus cycle is saved and could take place even if CPU is halted by antic

* additional useful instructions are added on the places where the unstable "illegal instructions" reside

* it could also make sense to support the stack area inside the CPU replacement, saving the external bus cycles for stack operations (imagine a single cycle "RTS")

 

The drawback is only a moderate acceleration (I guess about 20-30%), but the quite high compatibility (as it is unusual to let ANTIC access the zero-page or stack) and simple plug-in installation would be IMHO very interesting anyway.

 

It could maybe be possible to switch also to the 65C02 instruction set.

Why break C02, C802 and C816 compatibility? That is just STUPID!



#45 Irgendwer OFFLINE  

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Posted Sun Sep 9, 2018 4:17 AM

Why break C02, C802 and C816 compatibility? That is just STUPID!

 

I know that you are quite emotional about this subject. But having the first time a CPU accelerator which is fully compatible to the 6502C instruction set, is something I wouldn't call "STUPID" - even if you fear that compatibility support of your beloved C816 is weakened then (I don't share this view, if someone likes to break compatibility, he could already today).



#46 Irgendwer OFFLINE  

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Posted Sun Sep 9, 2018 4:20 AM

Or a 8080/Z80. And run CP/M.

 

...or Spectrum titles.



#47 Heaven/TQA OFFLINE  

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Posted Sun Sep 9, 2018 7:51 AM

 
An upgraded version of Sally would be very interesting. A 100% ("illegal"-) op-code compatible CPU replacement with turbo mode
(I already wrote that in another thread but for completeness again):
 
* A "special" instruction sequence enters turbo mode
* in turbo mode most single byte instruction take only a single cycle (e.g. INY, CLC, ROL)
* branches could be one cycle faster if taken as well as page breaking indirect accesses
* the zero-page RAM resides inside the CPU replacement, so that the zero page bus cycle is saved and could take place even if CPU is halted by antic
* additional useful instructions are added on the places where the unstable "illegal instructions" reside
* it could also make sense to support the stack area inside the CPU replacement, saving the external bus cycles for stack operations (imagine a single cycle "RTS")
 
The drawback is only a moderate acceleration (I guess about 20-30%), but the quite high compatibility (as it is unusual to let ANTIC access the zero-page or stack) and simple plug-in installation would be IMHO very interesting anyway.
 
It could maybe be possible to switch also to the 65C02 instruction set.


What about burst mode like the C64 DTV?

#48 Irgendwer OFFLINE  

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Posted Sun Sep 9, 2018 8:31 AM

What about burst mode like the C64 DTV?

 

AFAIK the burst mode relies on fast ram, which is able to transfer 8 bytes of data in a single cycle. As I would just replace the CPU and leave the rest of the system unchanged, this is IMHO out of sight.

Of course fast data transfers to the decoupled zero-page and stack are imaginable, but would require explicit use by new software.

As we do not drown in new titles I regard those features of an expansion not a necessity.







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