The p-code card contains 12 K of ROM and 48 K of GROM (8 chips).
CRU base address is 1F00H. The ROM is in DSR space, 4000-5FFFH. The last 4K (5000-5FFFH) are bank switched via CRU bit 1F80H.
The GROM address I don't remember without checking, but it down in the 5C00H-area. The address decoder for CPU address access decodes these addresses down to the specific words, so that normal code can use all other addresses.
The program on the p-code card includes instructions which transfer a large segment of startup code to 8 K RAM on startup, then more code and data to that area for operation. It also contains routines which move the inner part of the PME to RAM PAD (8300H) for faster execution. Parts of this code references data in DSR space.
To move it requires that either you can have it available in the same memory area, controlled by the same CRU bit, or you have to rewrite all code to respond to other addresses. Like if you want to run it in cartridge space instead. Note that there are several tables used to point to different code segments as well, so not only easily detected Branch instructions need to be changed.
You also have to allocate memory addresses for GROM access elsewhere than in DSR space, if you move it to cartridge space.