Has anybody documented the undefined behavior of the TMS9900 data and address buses when no memory cycle is happening?
I noticed this today while debugging a hardware glitch (unsuccessful so far): During the Add instruction, the databus repeats the two operand values.
I don't see this behavior documented in the TMS9900 manual. It seems like a nice feature to have. I guess it's the ALU "leaking" its values onto the data bus.
What does an Add instruction do? The sequence of operations is roughly:
fetch source operand
fetch destination operand
internal ALU cycle (in this case, ADD)
store destination operand
Here is an observed sample case where the cpu adds 0010 + dec8 = ded8:
PC 7d32 (whole program from 7d00 to 7d80)
Bus observations (each row is at least 1 clock cycle):
ADDR DATA Signals Action
7d32 a540 MEMEN DBIN IAQ read instruction: A R0,*R5
???? xx40 decode
???? xx10 decode
83e0 xx10 MEMEN DBIN fetch R0 from 83e0
a000 dec8 MEMEN DBIN fetch dec8 from a000
???? xxc8 internal
???? xx10 internal
a000 ded8 MEMEM WE store result to a000
xx are the high byte I can't see (I'm reading the side port. I only see one half of an internal 16 bit bus read.)
?? are addresses I missed cuz I only grab the address when MEMEN is asserted.
The internal cycle values xxc8 and xx10 match the destination and source values.
I'll be taking more notes on other instructions.