Ok, so Tim has put in my hands a Geneve that reproduces the problem with TIPI.
I've built a test cartridge that exercises the TIPI in GPL/ROMPAGE mode, and a corresponding python script.
What we see is that I cannot write to the 8 bit latches in the CPLD at 0x5FFD and 0x5FFF.
This is all I know so far, all the rest of TIPI works... reading from the latches set by the PI work fine, reading the ROM works fine, the crubits work fine.
I've been sitting on this for a while. but I have a lot of other things I want to do in my hobby life... So...
For the next 30 days, this will be my HOBBY priority. and if I do not have a solution by then, I am done. The only interest I have in getting it to work on other peoples' Geneves is gaining a little bit of knowledge.
But I need to make a good effort, and then admit defeat and move on, or rejoice in success! ( I am hoping for the latter )
I don't build TIPIs... I won't build TIPIs. So if the outcome requires physical changes, you'll all have to find someone to build them.
So, if you want this to work, now is a good time for you to learn how to read verilog, and assembly, and pester me.
Beery has been feeding me clues for a while... Given some of what he has fed me, and the lack of information out there, I'm going to start back at the prototyping process to figure out how to latch 8 bits in the DSR address space on write. Seems simple enough... But I have to pretend I don't know how to do it on a 4A or I'm trapped in the loop.
Interesting thing I read last night in the 9995 datasheet... the WE and CRU_CLK signal are the same pin...