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Coleco ADAM RAM Expansion options - Advice please


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#1 CharlesMouse OFFLINE  

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Posted Thu Mar 28, 2019 9:15 AM

Hello again.

 

I'm having fun banging out designs for ADAM doo-dads - maybe some of them will actually work!

 

Comments in another thread got me thinking; what about RAM expansion?

 

I've piggy-backed some IC's to my ADAM's current 64k to bring it up to 128k (or 144k if you like) but it seems the good old ADAM can do better...

 

...I've been trying to reverse engineer the board in the piccies. Sorry I can't remember what thread I found it on but it appealed to me as the design seems to potentially support stupid amounts of RAM - about 2mb? But a conjunction of 'missing' info and running out of brain has left me a bit stuck.

 

Can anyone point me in the direction of:

-The schematic for this board

failing that

-The schematics for any RAM expansion above 64k

failing that

-Better photos of this board's PCB (esp the IC side)

failing that

-Good photos of any RAM expansion above 64k

failing that

-Good info on how the ADAM actually addresses it's memory*

 

 

*obviously for an 8 bit system to be able to address so much RAM the ADAM must have a fairly advanced paging scheme.

 

Many thanks

 

 

Attached Thumbnails

  • post-10892-0-19357200-1545447183.jpg
  • post-10892-0-24238100-1545447117_thumb.jpg


#2 pearsoe ONLINE  

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Posted Thu Mar 28, 2019 1:00 PM

Here's the Micro Innovations schematics.

Attached Files



#3 CharlesMouse OFFLINE  

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Posted Thu Mar 28, 2019 2:35 PM

Here's the Micro Innovations schematics

Awesome!

 

Thank you so much, I really appreciate it. I'll go get my head down and see what I can make of it...

 

Out of curiosity:

I like to share my designs wherever possible in the hope they might be of use to others. As I'm now very likely to roll my own version of the schematics pearsoe has kindly posted does anyone currently own this design?

-If so I'll need to credit them

-If still a commercially available product I might need to keep any potential version of my own to myself.

 

Regardless thank you again. :-D



#4 NIAD OFFLINE  

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Posted Fri Mar 29, 2019 6:47 PM

I've been trying to reverse engineer the board in the piccies. Sorry I can't remember what thread I found it on but it appealed to me as the design seems to potentially support stupid amounts of RAM - about 2mb? But a conjunction of 'missing' info and running out of brain has left me a bit stuck.

The Memory Expander pictured was made for and distributed thru E&T Software (Ed Jenkins). It uses 256K SIPP Memory Modules and can be upgraded in increments of 256K all the way up to 1Mb. I tested out quite a number of these that we  sold thru NIAD, but they were always on a 256K populated board. I don't have much else to offer on this M.E.

 

Attached are full schematics, silk screen, etc., etc. for the Micro innovations lineup of Memory Expander.

 

Attached are pics of other Memory Expanders made for the ADAM... all install in Slot #3.

 

Hopefully the Micro Innovations tech files will provide the necessary info you need for the memory addressing.

Attached Thumbnails

  • MegaRAM Expandable Memory Expander with 1 256K SIPP.jpg
  • E&T Software 256K Memory Expander SIPP Module (100 nanosecond).gif
  • MicroFox 256k mem exp.jpg
  • 256K Memory Expander - Back #01.jpg
  • 256K Memory Expander - Front #01.jpg
  • 64K ME wire wrapped.jpg
  • 64K Memory Expander - #01.jpg

Attached Files



#5 CharlesMouse OFFLINE  

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Posted Sat Mar 30, 2019 10:15 AM

Thank you yet again. Much appreciated, I shall enjoy looking through those documents and trying to make sense of them.

 

Oh, and I really like those bread-board versions - very ghetto, my kind of work... at least before PCB fabrication became to cheap and easy.

 

Thank you indeed.

 

 

PS

Hopefully there will also be some confirmation as to which pin(s) are required from the middle slot to be able to shoot for more RAM... glad I've not sent off the gerberbers for my attempt at a serial / 80col board yet - hopefully I'll be able to add a header for a RAM board. 

 

PPS

I just had a quick peruse... I've got to say the Micro Innovations cards are very nicely designed. I may try to make my own 2mb card some day...

...but rather pleased to see there's (an admittedly untested) 1mb design using discrete logic - I've nothing against programmable logic but I find them to be a bit of a pain for one-off production:

Is the firmware good?

Did it program properly?

And following on I'm too cheap to by a proper GAL programmer so it's ghetto-time which is just a pain.

 

In short I think I'll have a go at a spin on that 1mb design. Hmm, still no confirmation on what middle slot pin is used by larger RAM boards... I think I'll need to have another look at some MI middle slot designs to get an idea.


Edited by CharlesMouse, Sat Mar 30, 2019 10:36 AM.


#6 ChildOfCv OFFLINE  

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Posted Sat Mar 30, 2019 12:29 PM

It seems to require two entire boards.  You can't just attach to a pin.  You have to decode the bus signals to find out when it's specifically talking to you about setting the memory page.  According to the instructions, it piggybacks off of another board such as the printer interface.

 

Also, the schematic seems to be a newer version of the board than what is pictured.  Your picture has 4 74ls157s and one 74ls175.  The schematic has 3 programmable logic chips.



#7 CharlesMouse OFFLINE  

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Posted Sat Mar 30, 2019 2:35 PM

Hi ChildOfCv,

You may well be right there... but I'm hoping I'll only need an extra addressing signal off the middle slot (J6).

My reasoning is as follows:

Having taken a good look at some of the higher capacity RAM boards, and the 4Mb E&T board in particular, they all seem to use very similar address decoding. Indeed, now I've seen the prototype MI board schematic (using 74 series logic) it's basically the same set-up as the E&T board.

Pictures of the E&T board show a jumper connector that looks very much like you would jam it in a slot, and while MI board's manual does indeed mention the need to connect to a board in the middle slot it also states this can be done with other manufacturer's middle slot boards - I therefore presume if said boards were doing more than just providing a missing signal MI couldn't guarantee the correct functionality from other vendor's devices and so wouldn't mention it as an option...

...having said that, could I be wrong? Absolutely. Do I know bog-all about the ADAM's architecture? Oh-yes.

 

FWIW: My odd way of familiarising myself with a system that's new to me is to (sympathetically) hack it.

 

With those caveats in mind here's my first stab at a 1Mb board based on the schematics kindly provided:

-It's based on the 'prototype' MI board

-I've replaced the four 256k SIPPs with four 256k static RAMs

-As a result I deleted the three 74LS157s...

...to my uneducated eye '175 and '138 look to be for address decoding and RAM selection while the '157s were needed to translate the ADAMs addressing to work with the SIPPs and so not needed to drive the static RAM chips I'm using.

 

Why 4x 256k instead of 1x1mb..?

Pure laziness on my part. It was easier to delete the ICs that the four RAM chips hopefully didn't need but leave the rest of the logic in place. Also as a small aside I have a bit of an aversion to plugging stuff in to old machines that dosen't quite look the part... modern boards tend to look too spartan when attached to old machines. 

 

 

Um, if anyone is kind enough to do a quick sanity check on what I've done, and indeed the assumptions I've made, I'd really appreciate it.

Attached Thumbnails

  • RAM_CARD_SCH.png
  • RAM_CARD_BRD.png

Edited by CharlesMouse, Sat Mar 30, 2019 2:39 PM.


#8 CharlesMouse OFFLINE  

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Posted Sat Mar 30, 2019 3:24 PM

Humble Pie Time:

 

ChildOfCv you were quite right. I've been going over the schematics and then the GAL code for one of the cards MI states is compatible with their RAM board...

 

MSTB = IORQ & WR & A[7..0]==42H

 

MSTB is the strobe signal used for bank selection with higher capacity cards.

but

IORQ & WR & A[7..0]==42H tells us it's as you said not just a signal 'missing' off the RAM expansion slot we're doing a bit of decoding with the Z80's IORQ and WR signals while, it seems using address lines A0-A7 for bank selection on Port 42H

 

 

Hmm

...so apart from a dose of humble pie I need to go away and find out:

-Where best to tap IORQ and WR, A0-A7 already being on the RAM slot

-How best to whip-up a bit of port decoding with some 74 series logic - hmm, more IC's I fear.

 

While I'm now sadly in to the realm of actually applying some effort to this plan I'd still appreciate a sanity check on the above board, thanks.


Edited by CharlesMouse, Sat Mar 30, 2019 3:26 PM.


#9 chart45 OFFLINE  

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Posted Sat Mar 30, 2019 4:41 PM

is there a problem when using the sgm and the extra ram in the adam cause 52h and 42h are very simillar

#10 ChildOfCv OFFLINE  

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Posted Sun Mar 31, 2019 3:14 AM

It looks like you plan to use 32Kx8 SRAM chips to bank switch between?

 

As for RAS and CAS, it seems possible, but I'll go ahead and talk about how the memory works.  If you already know this, feel free to skip :)

 

RAS and CAS are signals intended for DRAM.  Pretty much every DRAM chip in the world will divide its addresses between rows and columns of a matrix, about half and half.  One half of the address signals will be placed on the address bus, the RAS brought low.  At this time, the R/W signal also needs to be set accordingly, since as soon as CAS is signaled, the operation will commence.  Next, the other half of the address lines will be placed on the same address bus and the CAS brought low.  If it's a memory write, the new value will be placed into memory.  If it's a memory read, the value in memory will be placed on the data bus.  So for the sake of timing, you will see:

 

RAS, R/W set accordingly, then CAS.  RAS will be held low (active) for the entire period.

 

With SRAM, you of course need the entire address on the address bus.  Looking at a AS6C62256 data sheet, it does appear that the signaling will be compatible with the way you wired the chips.  On a memory read, you will see RAS, then R/W (low), then CAS.  The truth table on the data sheet says that when CS and WE are active, it doesn't care about OE, so on CAS this shouldn't cause the chip to seize control of the data lines (yay).  For reads, CS (RAS) comes first, WE (R/W) stays inactive, and OE (CAS) will signal data output.

 

So as long as you use a chip where OE is ignored on WE, this should work.

 

For future reference, I see that the memory slot gets a line called RA7 rather than BA7.  I am guessing that this has to do with memory refresh.  The Z80's refresh counter never changes the 7th bit, so it cannot refresh the entire 64K address space by itself.  Don't ask me why the engineers designed it that way, but that's just the state of things.  So they have a value from the MIOC (a custom IC that interfaces between the Z80 and the 6800's that litter the machine) that maintains a phantom 7th bit for refreshes.  The PLA maps that external flip-flop into bit 7 whenever RFSH is active.  When not on RFSH, this output matches BA7.  This becomes RA7.  (Maybe it stands for "Refresh Address 7").

 

Now, for technical information on how expansion RAM is even accessed, I found an Adam emulator and peeked at its code.

 

First of all, you have to configure memory banking by writing a value to port 0x60.  The bits are as follows:

xxxx xxNN  : Lower address space code.
      00 = Onboard ROM.  Can be switched between EOS and SmartWriter by output to port 0x20
      01 = Onboard RAM (lower 32K)
      10 = Expansion RAM.  Bank switch chosen by port 0x42
      11 = OS-7 and 24K RAM (ColecoVision mode)

xxxx NNxx  : Upper address space code.
      00 = Onboard RAM (upper 32K)
      01 = Expansion ROM (those extra ROM sockets)
      10 = Expansion RAM.  Bank switch chosen by port 0x42
      11 = Cartridge ROM (ColecoVision mode).

The upper nibble seems to be ignored entirely.

 

And as is already apparent, bank switching is done by writing a value to port 0x42.  Of course in the case of your 32K banks, the upper bank will just be a mirror of the lower bank.  The value of port 0x42 itself represents which 64K you want to see within the memory space.  It is always organized such that the first 32K of each bank maps to the lower 32K and the second 32K always maps to the upper 32K.  You can't map the second 32K into the lower 32K, or the first 32K into the upper 32K.  So this lets you bank up to 16M into this system.  Yikes.

 

As to how to decode 0x42 without an I/O card, the simplest solution does seem to be a hex inverter and a 4048 in OR mode.  Put bits 6 and 1 on the inverter.  Then along with the other bits, into the 4048 inputs.  IORQ goes to the EXPAND input.


Edited by ChildOfCv, Sun Mar 31, 2019 3:30 AM.


#11 CharlesMouse OFFLINE  

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Posted Sun Mar 31, 2019 10:07 AM

@chart45:

 

Ahh, yes. Clashing ports can be an issue. It often comes down to how lazy I am in decoding ports, and how lazy Coleco or other expansion manufacturers have been...

...in a nut-shell as long as everyone uses a different port and everyone has fully decoded said ports all is good. On the other hand you can skimp on ICs which generally results in decoding blocks of ports which can result on overlaps if everyone is doing that.

 

@ChildOfCv:

No worries on the information front. I really, really appreciate your taking the time to post so much very helpful information - I suspect you've given me a real leg-up on this project, especially as I'm going to have to put some thought in to it now.

 

On the subject of my choice of RAM IC's I'm glad you feel it looks to be appropriate. My decision-making was again based on laziness and knowing I'm not familiar with this computer:

-I need to replace the SIPPs with something more appropriate

-It would be best to retain the current decoding logic to reduce the chance I make a mistake

-As a bonus I'll get rid of the SIPP related logic

 

I could have gone with a single 1Mb SRAM but I'm trying to minimise mistakes & effort.

 

Again, thank you very much indeed. :-)

 

PS

Hex inverter and a 74048..?

I wouldn't have thought of such a neat solution, thank you. :-)


Edited by CharlesMouse, Sun Mar 31, 2019 10:48 AM.


#12 CharlesMouse OFFLINE  

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Posted Sun Mar 31, 2019 11:53 AM

PPS

...I meant CD4048. 



#13 CharlesMouse OFFLINE  

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Posted Sun Mar 31, 2019 4:13 PM

Right, another go:

 

Once again my sincere thanks for the most generous help. Here's another go with addition of the relevant logic.

 

Once again if anyone feels like doing a sanity check on my schematic I'd really appreciate it. I've included a .pdf of the 4048 datasheet for reference - I guess the main potential issue is my having misread the truth table for choosing the logic...

...or getting my MSB's and LSB's mixed up on A0-A7, I'm 'good' at that!

 

Assuming all is actually good, miracles can happen, the remaining issue is where to tap that pesky banking line? For those with appropriate middle-slot cards (not me) I've left the 'standard' selection line in place...

...and for those without there's a second point for a flying to attach to IORQ.

-Pin 7 Slot J7

-Pin 12 Slot J6

 

Not exactly convenient! I'll break out the old multimeter in a bit and see if there's a suitable passive that can be attached to.

Attached Thumbnails

  • ADAM_Mem_v2_SCH.png
  • ADAM_Mem_v2_BRD.png

Attached Files


Edited by CharlesMouse, Sun Mar 31, 2019 4:14 PM.


#14 tschak909 ONLINE  

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Posted Sun Mar 31, 2019 4:23 PM

Why not just take every conceivable peripheral possible and cram it onto one card? We can do that, now. I mean literally just... SRAM + Raspberry Pi interface, done.

 

-Thom



#15 ChildOfCv OFFLINE  

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Posted Mon Apr 1, 2019 12:56 AM

The ADAM makes that impossible.  The memory expansion port is the only one that gets the RAS signal.  The other two ports are the only ones that get the IORQ signal.  That's why all paged memory solutions are 2-card solutions.

 

With SRAM, you could get away with this since you don't care about RAS in that case.  But for DRAM, it has to be in the third slot.  Not just because you need RAS, but because you want the 7th refresh address bit too.


Edited by ChildOfCv, Mon Apr 1, 2019 1:02 AM.


#16 ChildOfCv OFFLINE  

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Posted Mon Apr 1, 2019 1:56 AM

One note:  If you hook up the clock directly, the 4048 should have output disabled.  So Kd should be selectable with a jumper.  If 1, there is IORQ decoding.  If 0, it is high impedance.



#17 CharlesMouse OFFLINE  

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Posted Mon Apr 1, 2019 5:10 AM

One note:  If you hook up the clock directly, the 4048 should have output disabled.  So Kd should be selectable with a jumper.  If 1, there is IORQ decoding.  If 0, it is high impedance.

:-)

Thank you again, yes I should do that. I can be a bit slap-dash.

 

Nearly there... Believing the ADAM to be a rather flaky beast I did have a decoupling cap for every IC but deleted all  but the RAM-caps this time as I was getting short of routing space on the footprint I made for myself. Here's hoping I don't end up regretting that.

 

 

Out of sheer masochism I use Eagle for board design. I did an ADAM.lbr file for the three expansion slots - not pretty but functional. I've attached it in case it's of use to anyone else.

 

PS

@tschak909:

FWIW a perfectly reasonable question but my limited understanding of the ADAM brings up three points

-ChildOfCv is of course bang on the money, why Coleco did this is beyond me

-To my eye there's a surprising lack of room for cards in the ADAM which limits the number of IC's that can be used

-I'm a rank amateur at this business. I'm always surprised when my designs work and do try to stay on the simple side 

Attached Files


Edited by CharlesMouse, Mon Apr 1, 2019 5:17 AM.


#18 CharlesMouse OFFLINE  

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Posted Mon Apr 1, 2019 7:57 AM

Okey-dokey;

Here's what I hope is the PCB fab ready version:

-Gerbers

-BOM

-Layout

-Schematic

 

...it looks like I'm going to be keeping Seeed busy with orders.

 

As usual I think it important to point out I barely know what I'm doing. Files are provided in case anyone else finds them useful but don't try to make your own until I've hopefully reported back that it works.

 

Once again my sincere thanks for all the help. :-)

 

PS

It looks like a convenient spot to pick up IORQ is the South end of R68 (to the left of the middle slot)

Attached Thumbnails

  • RAM_CARD_SCH.png
  • RAM_CARD_BRD.png

Attached Files


Edited by CharlesMouse, Mon Apr 1, 2019 8:06 AM.


#19 ChildOfCv OFFLINE  

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Posted Mon Apr 1, 2019 1:26 PM

One potential improvement once the initial prototype is finished, is to use a single 256Kx8 SRAM chip instead of the 4 32Kx8's.  Not only does that give you twice as much memory at a reasonable cost (like $3 per chip, and in PDIP package) as well as fully 64K mappable space, but it also lets you use the lower 2 bits of your bank select register as the upper 2 address bits on the SRAM.  You could still keep the 138 for multiple chips, based on the upper bits of the page register.  This would give you up to 1MB of SRAM capability.  The chips would likely have to be laid horizontally just like their controlling logic, though.


Edited by ChildOfCv, Mon Apr 1, 2019 1:27 PM.


#20 HDTV1080P OFFLINE  

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Posted Tue Apr 2, 2019 1:37 PM

It would be neat to own a 2MB or even a 128MB memory expander for the ADAM. A 64GB SDXC card is more faster then the ADAM computer and maybe there is a way to make a ADAM memory expander that uses a 64GB SDXC cards.

 

Its nice to see someone working on making a home made memory expander for the ADAM. If a 2MB or larger memory expander every went into production for the ADAM computer I would be interested in buying the memory expander.


Edited by HDTV1080P, Tue Apr 2, 2019 1:39 PM.





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