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Atari SIO transmission oscillogram


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#26 RockfordDash OFFLINE  

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Posted Sun Apr 21, 2019 9:53 AM

Hi Nezgar, as you wish... With and without caps, no extra resistor (in above post).



#27 HiassofT OFFLINE  

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Posted Sun Apr 21, 2019 10:28 AM

I don't understand how signal with caps present can rise so quickly that slope looks almost vertical. But I suppose level shifter has pull-ups too and a lot depends on it.

Did you have the diode in place in this test? The traces look a lot like it's missing - you have a steep rising edge from the push/pull outputs on the RPi up to 3V3 and then a slow rising edge from the pull-up resistor on the levelshifter up to 5V.

so long,

Hias

#28 RockfordDash OFFLINE  

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Posted Sun Apr 21, 2019 10:46 AM

I do have a diode in place. Signal is measured behind it, on SIO side.

 

Thanks,

RD



#29 ivop OFFLINE  

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Posted Sun Apr 21, 2019 11:37 AM

Please tell us more about this upgrade.
 
From what I remember, he put very fast schmitt triggers on data in/out and command of an SDrive. Maybe Mr. Atari can chime in. It was his friend that did this. I'm only faintly acquainted.


#30 HiassofT OFFLINE  

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Posted Sun Apr 21, 2019 11:46 AM

Some more traces of SIO data in (command ACK byte) with the pull-up removed

no caps:
div0-sio-data-in-ACK-no-caps-no-pullup.png

caps:
div0-sio-data-in-ACK-caps-no-pullup.png

and here a zoom-in on the first bit of the ACK plus in comparison zoomed in traces with the pull-up in place.

no pull up, no caps:
div0-sio-data-in-ACK-no-caps-no-pullup-closeup.png

pull up, no caps:
div0-sio-data-in-ACK-no-caps-pullup-closeup.png

no pull up, caps:
div0-sio-data-in-ACK-caps-no-pullup-closeup.png

pull up, caps:
div0-sio-data-in-ACK-caps-pullup-closeup.png

so long,

Hias

#31 ricortes ONLINE  

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Posted Sun Apr 21, 2019 12:18 PM

IDK. I think one of the things I subscribe to is a robust design as long as it isn't me that is doing the design. j/k What I said about a Schmitt trigger is true but properly chosen and placed it would let people hang 3-4 drives, an 850, RPi, et al on the SIO chain and still work. Wouldn't be needed for a single drop device of course.

 

In my experience the more complex the design the fewer people that can execute it. Anything above ~14 pins and half the people out there can't get it done. Even the RPi according to the link provides 50k pull ups if my cursory reading got it right.

 

Some of the things we have to worry about are future devices that may use CMOS and 2.5V switching levels. Buffered and fast rise times to 2.5V would be a good thing. On the other hand, the old equipment is slowly wearing out. The new stuff, SDrive, RPi, SIO2PC USB, all don't load the lines that bad when used alone and even the old stuff like 1050's buffered in the device. Just me, I'm not going to worry about it until a problem pops up. I mean something like a POKEY replacement in CPLD that runs at 40 MHz and outputs serial data at 1 MHz or something. What we have now, cutting caps & pull up, is good enough. Heck, I like this discussion; moves me to think.

 

For the new stuff, it would be best to have a buffer included, SIO through second plug, aux 5V supply that is isolated from the computer but supplies a couple of amps on the 5V line, and "Plug me in first" so everything down stream would get clean signals and juice. Probably more stuff I am missing these things would be nice. 



#32 DrVenkman ONLINE  

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Posted Sun Apr 21, 2019 12:55 PM

Hias -

 

I'm curious; how are you capturing the SIO traces? Not how you're triggering the scope, I mean physically connecting things. Do you have a breadboard or something rigged to plug into the SIO chain to clip your scope probes to, or are you actually grabbing signals from POKEY, SIO port or some other points on the Atari?



#33 HiassofT OFFLINE  

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Posted Sun Apr 21, 2019 1:18 PM

In these tests I used my self-built serial SIO2PC interface where I added a 0.1" header so I can easily access the SIO signals.

When I tested with the RPi and level shifter some time ago I used the SIO part of the PCB of a dead 1020 which I sawed off. Also with some headers added so I can easily grab signals. A picture of that is here: http://www.abbuc.de/...3&t=9715#p80170(the second SIO connector from that PCB now lives in my eclaire daugherboard, if it would still be there that PCB could serve as an easy method to get signals from a SIO chain).

On other occasions I grabbed signals directly from the SIO port inside the Atari, one time I soldered headers into the holes of the (removed) SIO caps on the in/out/cmd lines - then I could attach dupont wires and have the keyboard of my 800XL in place.

so long,

Hias

Edited by HiassofT, Sun Apr 21, 2019 1:27 PM.


#34 ivop OFFLINE  

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Posted Sun Apr 21, 2019 3:33 PM

I have something similar. Here's an image I posted earlier: http://atariage.com/...-2#entry3853733

 

All SIO signals are available on two straight and one angled header.



#35 Nezgar ONLINE  

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Posted Sun Apr 21, 2019 3:34 PM

Thanks for the additional visuals!
 
I've disconnected the caps in a couple of my machines, but didn't add the 4k7 resistor. (yet) I can see the resistor appears to be just a small incremental improvement over disconnecting the caps. Will still look into adding the resistor when I'm next working on the machines though. I honestly haven't done much faster than divisor 3 or 4, but mostly because that's the upper limit of the SpartaDOS UltraSpeed handlers. Will have to try pushing it further with the HiassofT patched OS.

#36 _The Doctor__ ONLINE  

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Posted Sun Apr 21, 2019 3:47 PM

use the pclink driver with respeqt and see if that doesn't take you to divisor zero under spartados x. :)



#37 Nezgar ONLINE  

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Posted Sun Apr 21, 2019 10:54 PM

use the pclink driver with respeqt and see if that doesn't take you to divisor zero under spartados x. :)

 

With PCLINK, and a Lotharek SIO2PC-USB plugged to the back of 1 1050 (this one still has it's own speed limiting caps present) which is then chained to the Atari, I can reliably transfer at divisor 3. divisor 2 barfs.

 

And also same with the Lotharek SIO2PC-USB directly plugged to the 800XL, Divisor 3 works, Divisor 2 barfs. (Can't even get directory)

 

But... this is using SpartaDOS 4.49c's own highspeed SIO driver which I was thinking 3 was the limit. To prevent SDX from loading it's own drivers and use the OS based SIO drivers

 

I just created a custom CONFIG.SYS with SIO.SYS /A to use the OS based Hias HSIO routines, and found it also only functions up to divisor 3. PCLINK drives only work at 19200, probably because the OS handler doesn't recognize those drives...

 

So I wonder if the 4k7 resistor will help here?



#38 Nezgar ONLINE  

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Posted Mon Apr 22, 2019 1:00 AM

An update. Finally put the 4k7 resistor in. I didn't feel like lifting my 'main driver' 800XL's motherboard out of the case since there's things attached to the case, so with some continuity testing I figured out where I could install the resistor on the top side.  :-D  Connect the 4k7 resistor between the right side of C78 to top side of C80.

 

Some quick testing showed no improvement with SDX 4.49c native drivers, divisor 3 max. Sometimes I can get PCLINK.SYS to copy a file at divisor 2, but takes a few retries and NAKs and hangs.

 

Using SIO.SYS /A in config.sys (To access OS based Hias SIO patch) now lets me access normal ATR based RespeQt ATR media at divisor 0 reliably. However, PCLINK.SYS access only operates at 19200 in this mode.

 

So I guess the hardware works, but the software is kinda finicky. :D

Attached Thumbnails

  • 4k7.jpg


#39 HiassofT OFFLINE  

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Posted Mon Apr 22, 2019 5:28 AM

Using SIO.SYS /A in config.sys (To access OS based Hias SIO patch) now lets me access normal ATR based RespeQt ATR media at divisor 0 reliably. However, PCLINK.SYS access only operates at 19200 in this mode.

Good to hear this is working now!

My OS SIO patch only accelerates D1:-D8:, so PCLINK will run at standard speed - so the result is to be expected. If you have a U1MB you could try using it's PBI SIO driver, IIRC this will accelerate PCLINK as well.

I had a look at the SIO connection part of the 1050 schematics:
1050-sio.png

The caps C56,C57,C58 (which are recommended to be clipped off) create a path from SIO data in to ground (C61 which is also recommeded to be removed is behind the CA3086's transistors so won't affect the SIO bus directly). With a 4k7 resistor in series and a total capacitance of about 19pF that won't be a huge load - though it'll still affect the SIO bus even if the drive is powered off.

I also measured the parasitic capacitance of a SIO cable (between SIO data in/out lines and GND lines) and got about 110pF.

So the worst "offender" seems to be the 1nF caps in the Atari, followed by SIO cable, then parasitic capacitance in the SIO device (like the caps in the 1050), each about one order of magnitude apart.

The additional pull-up may help a bit in extreme cases (caps in the Atari plus a few SIO devices connected), but I'd guess a similar pull-up would be needed on SIO data out as well.

so long,

Hias

#40 flashjazzcat ONLINE  

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Posted Mon Apr 22, 2019 9:05 AM

Yes: the U1MB PBI implementation of Hias' driver can optionally handle the PCLINK device, and does away with the need for the /A switch in CONFIG.SYS. I never had any luck with divisor 0 using the SDX SIO driver, but I use the U1MB driver at 127Kb/s 100 per cent of the time without a single problem.

#41 ricortes ONLINE  

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Posted Mon Apr 22, 2019 2:52 PM

Would have been nice to have that LM3086 under the hood in our Atari. I just looked at the data sheet and it will handle 300 mWatt/transistor up into the VHF range. It is more complex then a simple design like a ~hex Schmitt trigger but fan out and frequency response would have been hails. Min Hfe is 40 so if you really wanted to drive a herd of stuff on the SIO chain, that would be the way to do it.

 

I do know people that had Atari back in the day. For some of them the extra expense would have been pointless. They just had Atari 400s and the only thing they used were carts and joysticks. 



#42 Kyle22 OFFLINE  

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Posted Mon Apr 22, 2019 6:23 PM

Yes: the U1MB PBI implementation of Hias' driver can optionally handle the PCLINK device, and does away with the need for the /A switch in CONFIG.SYS. I never had any luck with divisor 0 using the SDX SIO driver, but I use the U1MB driver at 127Kb/s 100 per cent of the time without a single problem.

 

Same thing exactly here on the Incognito PBI BIOS. It's flawless.






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