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mono

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  1. @neuling: h- may be insufficient if you need the continuous memory area. Take a look at f+ opt switch and b- if your (cartridge) memory is banked (rmb/nmb/lmb directives and =label as well as :label references are helpful for such model).
  2. Yes. It works with POKEYMAX if it has SID emulation inside. This player is not released yet, however it was created a years ago. I'll plan to do this in the near future.
  3. Yes, there is an picture made by Irwin years ago named "Impossible is nothing" https://demozoo.org/graphics/62641/.
  4. Exactly. I'm pushing pixel pattern at Virtual DMA cycle using BIT $x0 or BIT $x0x0 instruction as @phaeron already explained. Also I've implemented 240-hires scanlines bugfix using your algorithm. So, as you can see I didn't invent anything, but just sit and did the job @phaeron Thanks a million for your "Altirra Hardware Reference Manual" - I studied its ANTIC scanline diagrams for different modes. It's very helpful.
  5. On the page 77 in the section "Dynamic changes to playfield width" - there is "The playfield width bits in DMACTL[1:0], and the horizontal scroll position bits in HSCROL[3:1](...)", but I think it should be HSCROL[3:0].
  6. Altirra Hardware Reference Manual released at 2023-10-09. On page 70 in section "Mode lines unusual height" we have got "For IR mode 2, rows 8-9 are blanked for characters $00-5F and $80-BF(...)" - shouldn't it be $DF?
  7. Congratulation for the winners! I voted Buddy's "Unexpectedly Short" however, and was in big trouble if choose this one or "Pokey Atmosphere". Could you consider future compo where rating vote is possible? Thanks a lot for all this music and for compo!
  8. XEDISK by Epi: https://github.com/epi/xedisk FRANNY by Bober: https://sourceforge.net/projects/atari8/files/franny/Franny-1.1.3/
  9. @Mr Robot: Could you share your ATASCII Art source or binary (.xex) file?
  10. Could somebody share original Logiker's .asc or .psci logo files for 2nd and 1st editions of ATASCII Compo? Edit: Or .xex files.
  11. Thanks a lot. I thought it's more complex and there is no signal under special circumstances, even though it should be there.
  12. I mean what signal, looking from the outside of computer, is present or expected on SIO Clock In (BCLK) and SIO Clock Out (ACLK) in specific SIO clock mode/configuration.
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