netdude77479

I am interested in attending future meetings. gary_L_becker@yahoo.com

One use for the /RDY pin is to streach accesses to slow devices. During the time /RDY is asserted, the 6502 address, R/W, and data bus on writes is kept enabled. The 6809E does not have a /RDY pin, so my method of adding this feature was to stop the clock going to the 6809E. If I used the 6809E TSC, the buses would go away. The 6809E /HALT pin was not usable either. It only stops execution during the last cycle of the instruction. Gary

Thanks again Bob. 01 and 02 driven from the circuit to the main board is not stopped. The Q and E clocks driven to the 6809E are stopped for the RDY signal. I believe the RDY is not needed. It might cause issues with the 6809E if RDY is asserted for long enought time. It looks like the Halt can be directly connected to the 6809E TSC (tristate) pin. This will tristate the address and data buses for a cycle or longer. Gary

Thanks for the info Bob. I believe I understand the timing. The Halt signal on the 6809E will not work for this, but there is a tristate pin I can use. When you mentioned the rise and fall of 02, does that mean Sally continues to drive the clocks? Or do you mean 00. the input clock to Sally which is nearly identical to 02? Gary

Let me introduce myself. My name is Gary Becker. I am helping Boisy in his XEGS project. I have a lot of experience with the 6502, but it has been a few years ago. I do not have any experience with Atari's Sally version. I also have experience with the 6809E. I generated the schematic Boisy posted. I am now working on adapting other signals. I understand Sally has a Halt input. The Halt signal on the 6809E will tristate the address and data bus during the last cycle of the current instruction. I found some information on the Antic chip that gave me some information about the Halt signal and how DMA is accomplished. It appears to me the Antic will expect to be able to grab the bus on the next CPU cycle after asserting the Halt signal. Is this correct? That is not the way the 6809E will do it. It could be easily be 5 or more cycles before the 6809E goes into halt mode. Another question is with the clocks. The PHI 1 and PHI 2 clocks are output from the Sally chip, but the Q and E clocks are inputs to the 6809. During halt mode, does the Sally chip tristate these clocks? Sorry for having to ask so many questions on my very first post. I look forward to getting to know the Atari systems better.