Would you mind to create waveform for CHBASE update, please? Starting from the external addr and data bus down to the CHBASE register including wrCHBASE signal? If not too complicated ideally with horizontal counter. With whatever values, only to have click ticks "numbered".
Theory: if CPU writes to CHBASE at the same clock tick when chAddrOe is active (to fetch character data from charset) this value is not used as it is at that time stored in the internal buffers and CHBASE is updated one clock later due to delayed wrCHBASE (passing S01/S02). Correct? (there is still nPHI2 involved, but I hope this can be ignored for this case )
If this is true, there is tricky question. If a CPU write happens exactly one clock tick before chAddrOe; is new, by CPU provided, or old, from CHBASE, value used to set A9/10-15? CHBASE update and addr bus set happens at the same S02 edge...