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msh

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  1. @phaeron you are correct that the mScanOe is not blocked. However this signal is moving address to the internal buffer only, not the the output pins (as @ijor kindly explained to me few responses before). The ultimate (and as far as I can see the only) signal to update physical address bus is AddrOe and in the schema on page #1 where the HALT pin is shown you can see AddrOe is parallel to HALT, only 1/2 clock delayed. As HALT is not set due to pfDmaReq not being set physical address is not updated. It is hard to say if this unnecessary population of address buffer can have any side effect, but I doubt it. I would guess the buffer is meant only to keep prepared address and then wait for AddrOe signal.
  2. This all really valuable feedback. I understand in the clock-ticks world there will be always one latest moment (tick) when the input matters. I assume there is happening some additional timing withing the tick, makes sense. I would be really sad to learn there are situations within ANTIC when the behavior is "random". Anyways, my primary objective is to be able to read the schema at a level to answer my questions (like the last tick which matters for CHBASE update) myself. Could be too ambitious for me, who knows Looking at the waveform provided I am curious why is the wrCHBASE only 1/2 clock wide? Address bus seems to keep value for full cycle. Other signals are 1 or 2 clocks wide. I want to double-check. At 32.5/33 there is missing update of D(ATA)BUS with character's $21 data. I think it is just "typo". I made a Photoshoped version with A0-15out signals. Is my picture accurate? This would make it very clean, only A0-15out would be updated on rising edge of S02 while everything else is happening on falling edge...
  3. Would you mind to create waveform for CHBASE update, please? Starting from the external addr and data bus down to the CHBASE register including wrCHBASE signal? If not too complicated ideally with horizontal counter. With whatever values, only to have click ticks "numbered". Theory: if CPU writes to CHBASE at the same clock tick when chAddrOe is active (to fetch character data from charset) this value is not used as it is at that time stored in the internal buffers and CHBASE is updated one clock later due to delayed wrCHBASE (passing S01/S02). Correct? (there is still nPHI2 involved, but I hope this can be ignored for this case ) If this is true, there is tricky question. If a CPU write happens exactly one clock tick before chAddrOe; is new, by CPU provided, or old, from CHBASE, value used to set A9/10-15? CHBASE update and addr bus set happens at the same S02 edge...
  4. Wow! this is so nice picture and explanation. There are some important bits of information I was not aware of signals like DlReq_1 do not do anything directly. These are just "enablers". The change is happening on S02 descending edge. I didn't expect DMA is instantaneous. At the same edge both address and data bus are set. I assumed something like: 1st edge sets address; 2nd edge retrieves data from memory chip. cycle 14 must have precise timing "within" the edge. DLL is updated at the same moment when data bus is being updated from $20 => $60. I would expect this to be hazard state, not by design This works due to some real-world/analog characteristics, or this is clear from the schema? actually the same is happening at cycle 15 - DLH is updated during change $60 => $FF Is there any reason why some of the signals in the picture are dashed? Just curious
  5. Thank you for the details how the chip works. I would have one more question about the symbols. There are "NOT elements" with extra signal connected to the "body" of the element. e.g. when plySngOe, plyDblOe or DlReq-1 is generated (pg.4). What does it mean? In some places the signal is input in some inverted input. And another one about high level funkcionality - display list jump operation. It is pretty complex, so not about the whole stuff. The part I cannot understand at all is how DL counter is updated with a new address. There is DlReq-1 signal to push DL counter to the address bus and to increment the counter at the same time. There are signals to update DLH and DLL from data bus derived directly from horizontal counter. But I am missing any kind of temporary storage for DLL data as I cannot update DL counter immediately with DLL I read. This would produce address [DLHold; DLLnew] and I would read DLH from invalid address. Not to mention there happens DL auto-increment too. I hope I am making sense. Not sure how to describe it better. I was thinking may be the DLL is left "floating" on the address bus between the two clocks? But this seems too crazy to me.
  6. Oh my! You are of course right. Such a stupid mistake on my side. I took it granted, not sure why, the address is prepared "positive way", and this is actually NANDs everywhere... Thanks for pointing this out.
  7. Hi phaeron, thank you for your response. If I got you right following diagram 'in---NOT---(S01)---out' can be understood as simple negation 'out = NOT in', provided this is during the "specific clock phase". Then this diagram 'in---(S02)---NOT---(S01)---NOT---out' where 'S02 = not S01' should work as signal delay 'out(t) = in(t-1)'. Did I get it right? I completely agree with your explanation of DMA signals. I was confused by unexpected horizontal counter values for DMAs and completely missed the 'nSpcDma' gate signal. Now I have much better picture of this part. This is great, thank you. Still, if I follow your explanation about the P/M address it works nicely in your email, but I cannot see support for this in the schema. e.g. you say "A10/A9: not hpos[2]" and in the schema I see "nHrz2---(S01)---NOT---pHrz2---A10/A9" I read it 'pHrz2 = not nHrz2' => pHrz2 is the same as Hrz2 (not sure why there is used 'p' prefix). It means in your notation "A10/A9: hpos[2]" and this doesn't work. Not sure what I am missing here?
  8. Hi all. I have find out this thread with the ANTIC schematic available. I am so exited this was created! I am checking the schema and trying to understand some of the ANTIC behavior. Unfortunately I am successful only partially. On high level I can see support for lot of ANTIC functionality I know about. On the other hand when I try to go to deeper details I am failing to verify ANTIC behavior. As a good example of what I cannot figure-out is sprites data reading. It should happen at the beginning of scan-line together with display list reading. I can see (pg.4 in PLAYER MISSILES AND DISPLAY LIST CONTROL) how bit Hrz0-2 of horizontal counter are connected to the address bus A8-10. I can see as well that the rest of address is coming from PMBASE and VCOUNTER. This is what I called above the "high level" of functionality confirmation I can do. However if I try to verify how A8-10 is evaluated out from Hrz0-2 I fail and and the address calculated by me for the first 8 cycles of scan line is not what it supposed to be. I assume my problem is in not understanding how nHrzX is transformed to pHrzX/pnHrzX and what does it mean when the signal goes through "circle connected to S01" (S01 I understand as clock signal) I have been struggling with this quite a lot w/o success Please would somebody be able to help me to understand how this particular fragment of the ANTIC schema works? I hope this helps me to read other parts too
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