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HiassofT

Member Since 3 May 2006
ONLINE Last Active Today, 11:39 AM

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In Topic: Atari SIO transmission oscillogram

Today, 5:28 AM

Using SIO.SYS /A in config.sys (To access OS based Hias SIO patch) now lets me access normal ATR based RespeQt ATR media at divisor 0 reliably. However, PCLINK.SYS access only operates at 19200 in this mode.

Good to hear this is working now!

My OS SIO patch only accelerates D1:-D8:, so PCLINK will run at standard speed - so the result is to be expected. If you have a U1MB you could try using it's PBI SIO driver, IIRC this will accelerate PCLINK as well.

I had a look at the SIO connection part of the 1050 schematics:
Attached File  1050-sio.png   217.49KB   1 downloads

The caps C56,C57,C58 (which are recommended to be clipped off) create a path from SIO data in to ground (C61 which is also recommeded to be removed is behind the CA3086's transistors so won't affect the SIO bus directly). With a 4k7 resistor in series and a total capacitance of about 19pF that won't be a huge load - though it'll still affect the SIO bus even if the drive is powered off.

I also measured the parasitic capacitance of a SIO cable (between SIO data in/out lines and GND lines) and got about 110pF.

So the worst "offender" seems to be the 1nF caps in the Atari, followed by SIO cable, then parasitic capacitance in the SIO device (like the caps in the 1050), each about one order of magnitude apart.

The additional pull-up may help a bit in extreme cases (caps in the Atari plus a few SIO devices connected), but I'd guess a similar pull-up would be needed on SIO data out as well.

so long,

Hias

In Topic: Atari SIO transmission oscillogram

Yesterday, 1:18 PM

In these tests I used my self-built serial SIO2PC interface where I added a 0.1" header so I can easily access the SIO signals.

When I tested with the RPi and level shifter some time ago I used the SIO part of the PCB of a dead 1020 which I sawed off. Also with some headers added so I can easily grab signals. A picture of that is here: http://www.abbuc.de/...3&t=9715#p80170(the second SIO connector from that PCB now lives in my eclaire daugherboard, if it would still be there that PCB could serve as an easy method to get signals from a SIO chain).

On other occasions I grabbed signals directly from the SIO port inside the Atari, one time I soldered headers into the holes of the (removed) SIO caps on the in/out/cmd lines - then I could attach dupont wires and have the keyboard of my 800XL in place.

so long,

Hias

In Topic: Atari SIO transmission oscillogram

Yesterday, 11:46 AM

Some more traces of SIO data in (command ACK byte) with the pull-up removed

no caps:
Attached File  div0-sio-data-in-ACK-no-caps-no-pullup.png   9.99KB   0 downloads

caps:
Attached File  div0-sio-data-in-ACK-caps-no-pullup.png   10.6KB   0 downloads

and here a zoom-in on the first bit of the ACK plus in comparison zoomed in traces with the pull-up in place.

no pull up, no caps:
Attached File  div0-sio-data-in-ACK-no-caps-no-pullup-closeup.png   8.92KB   0 downloads

pull up, no caps:
Attached File  div0-sio-data-in-ACK-no-caps-pullup-closeup.png   8.9KB   0 downloads

no pull up, caps:
Attached File  div0-sio-data-in-ACK-caps-no-pullup-closeup.png   9.14KB   0 downloads

pull up, caps:
Attached File  div0-sio-data-in-ACK-caps-pullup-closeup.png   9.11KB   0 downloads

so long,

Hias

In Topic: Atari SIO transmission oscillogram

Yesterday, 10:28 AM

I don't understand how signal with caps present can rise so quickly that slope looks almost vertical. But I suppose level shifter has pull-ups too and a lot depends on it.

Did you have the diode in place in this test? The traces look a lot like it's missing - you have a steep rising edge from the push/pull outputs on the RPi up to 3V3 and then a slow rising edge from the pull-up resistor on the levelshifter up to 5V.

so long,

Hias

In Topic: Atari SIO transmission oscillogram

Yesterday, 5:15 AM

I did some tests with my serial SIO2PC interface (MAX232, diode plus 4k7 pull-up on SIO data in). Only the SIO2PC and an 800XL were on the SIO chain and the cable was rather short (~15cm) and I tested at pokey divisor 0 (~125kbps).

First on an 800XL with the caps in place:

SIO data out, first byte of command frame:
Attached File  div0-sio-data-out-CMD-caps.png   12.92KB   0 downloads


SIO data in, command frame ACK
Attached File  div0-sio-data-in-ACK-caps.png   11.82KB   0 downloads

Then on an 800XL with the caps removed:

SIO data out, first byte of command frame:
Attached File  div0-sio-data-out-CMD-no-caps.png   12.85KB   0 downloads

SIO data in, command frame ACK
Attached File  div0-sio-data-in-ACK-no-caps.png   12.3KB   0 downloads

So, with the caps in place the additional 4k7 pull-up on data-in indeed improves signal rise time (whether that's actually needed is another thing). Compared to SIO data out even single 1-bits make it near 5V whereas on SIO data out the edges are less steep and the signal only goes to about 4V.

Compared to the measurements with the caps removed (with about perfect signal quality) one can see though that the signal high time (at the typical threshold of about 1.5V) is significantly shorter (especially on SIO data out). This means the headroom for variations in baud rates is smaller, too, which can be a problem in some cases (PAL and NTSC rates are a tad different, UARTs usually can't be configured to exact Atari baudrates or may have jittery clocks - like I saw on the Lotharek SIO2PC USB interface).

So, instead of trying to doctor around symptoms with schmitt triggers (whcih can't compensate for the shorter signal high time) it's better to just remove the caps if you want good signal quality and reliable highspeed transmission. If you add more devices to the SIO chain with additional caps in place (like a bunch of 1050ies) things will get a lot worse.

so long,

Hias